Raytheon DIDS-400 Series Technical Manual page 137

DIDS-402-2AM13
ter entry register, SDL goes high. SDL enables NAND-gate ASO. 6 and the D3
GATE flip-flop. When this occurs, seven additional clock pulses shift the char-
acter held in D3 into the delay line via NAND-gate A2S. 6.
When a control code is received as part of a data message, the D3 decode
circuitry is employed to determine the conditions surrounding the reception
of the code. These decodes, as well as the ESC and CCC flip-flops, are
discussed in paragraph 4-22.4.4 and illustrated in Raytheon Drawing No. 408025
and figure 4-35.
In the transmit mode, Initialize Transrn.it jams each flip-flop of D3 to reset
to insert a NULL character (0000000) into the register. Up to 16 ms later,
Enter Header jams flip-flop A20. 9 set to insert an STX code (0000010) into the
register. Enter Header also jams BB3 to indicate a D3 full status. After a
second l6-ms delay, T goes high and the combination of T and BB3
develo~
0A gate to start the 10-bit decimal counter. When the counter steps from STP
to STT, a start bit is placed on the transrn.itted data line through NOR-gate A37. 8.
On the next phase A pulse, the counter steps from STT and gate AS3. 6 is enabled.
This simultaneously enables NAND-gate A47.6 and A48.l2. Seven phase A
pulses are enabled through A47.6 which shift the character (STX) onto the trans-
mitted data line. Simultaneously, the character is applied to the parity check and
gen~ion
circuit (see paragraph 4-22.3.2). When the decimal counter reaches
the PAR count, the output of A53.6 goes low to inhibit gates A47.6 and A48.l2.
The result of the parity check is then gated onto the transmitted data line through
NOR-gate A37. 8 and the interface circuits.
The transmission of STX from D3 (or any other character) takes 8.33 ms
to accomplish. The cursor, which is circulating through memory attached to the
first character of the message, mayor may not appear in the character entry
register during the 8. 33-ms time interval. As previously stated, locating the
cursor results in simultaneously shifting a character into Dl and automatically
stepping the cursor one position to the right (CRQ).
Assuming that the cursor is not found during the time it takes to transmit
STX, the momentary status of the buffer registers is Dl-empty, D2-DA,
D3-empty. BB3, which is reset during the parity count of the transmitted
character, goes low to enable SG23-. This, in turn, enables the application of
seven
fast-clo~ulses
through A49. 6 which shift DA from D2 to D3. With
the conditions BBl, BB2, and BB3, DA is shifted out of D3 when NAND-gate
A47.6 is enabled. Before DA can be completely shifted out of D3, the cursor is
located and a character is extracted from the delay line. (There is a 646-fJ.s
difference between the memory access time of 16.026 ms and the two-character
transmission time, 16.660 ms). The character extracted from the delay line is
shifted straight through Dl and into D2 due to SDL
setti~BBl,
thus enabling
SG12. Since SG12 will shift the character out of Dl, a BBI is present after
13 fJ.s and the second successive character is shifted out of the delay line. Thus,
after approximately 26 fJ.s have elapsed, DA is still in D3, 1 st text is in D2, and
2nd text is in Dl. This condition (BBI, BB2 and BB3) disables SDL and the
cursor is released. After 16 ms it once again appears and another character
(or possibly two) is extracted from the delay line.
4-91