Pulse Width Modulation Output - Advantech PCI-1716 User Manual

The output can be gated. If counter gate is in active level, pulses are output normally.
On the other hand, if counter gate is in inactive level, output is disabled. Figure 3.40
shows an example of active high gate.
Figure 3.40 Gated timer/pulse output.
3.5.5

Pulse Width Modulation Output

In pulse width modulation output mode, a pulse waveform with specified high period
(tHIGH) and low period (tLOW) is output at counter output terminal as shown in Fig-
ure 3.41.
Figure 3.41 Pulse width modulation output.
The output can be gated. If counter gate is high, pulses are output normally. On the
other hand, if counter gate is low, output is disabled. This is shown in Figure 3.42.
Figure 3.42 Gated pulse width modulation output.
41 PCI-1716_Series User Manual