Counter Input Signal Connection - Advantech PCI-1716 User Manual

2.8

Counter Input Signal Connection

The voltage logic level between the counter input (counter clock, counter gate,
counter arm, and sample clock) terminals and the digital ground (DGND) terminal is
measured. To prevent undetermined or fluctuating results when input is floating, the
counter input signals are internally pulled-up. This is shown in Figure 2.11.
Figure 2.11 Counter input signal connection.
The input voltage must be either higher than the minimum value of ON state or lower
than the maximum value of OFF state for deterministic result. If the input voltage is
between these two values, the result is undetermined, which may be ON or OFF. In
addition, do not input a voltage higher than the maximum allowable value of ON state
or lower than the minimum allowable value of OFF state. The device may be dam-
aged under such circumstance. Refer to the device specifications for ON and OFF
state voltage ranges.
The counter input signals can also sense the status of an external switch. The status
of an external switch which is connected between the counter input terminals and the
DGND terminal is sensed as shown in Figure 2.12.
Figure 2.12 Counter input signal connection using a switch with internally
pulled-up.
19 PCI-1716_Series User Manual