Digital Input; Digital Output - Advantech PCIE-1751 User Manual

A.1

Digital Input

Table A.1: Digital Input
Input type
Input logic level
Input protection voltage -0.5 V ~ 6.5 V
Pull-up resistor
Response time
Debounce filter
Acquisition type
Interrupt
A.2

Digital Output

Table A.2: Digital Output
Output type
Power-on state
Output logic level
Load current
Response time
Update type
Initial output value
PCIE-1751 User Manual
5 V TTL
Logic high
Logic low
Working voltage
10 kΩ
25 ns max.
32 ns ~ 67 ms, software-configurable
Instant, software-configurable
Edge detection
Pattern match detection
State latch
5 V TTL
Logic low
Logic high
Logic low
One channel
Per port summed
25 ns max.
Static software-configurable
Software-configurable
24
2.0 V min.
0.8 V max.
-0.25 V ~ 5.25 V
Rising edge, falling edge, or both
edges, software-configurable per
channel
By port detection, each channel can be
enabled or disabled by software inde-
pendently
Latch port state when interrupt occurs
4.0 V min. @ 2 mA source / 5.2 V max.
0.4 V max. @ 2 mA sink
8 mA max.
20 mA max.