Digital Output; Digital Output Data Generation Methods - Advantech PCI-1716 User Manual

3.4

Digital Output

3.4.1

Digital Output Data Generation Methods

The device supports both static (software-timed) digital output update and buffered
(hardware-timed) digital output generation.
3.4.1.1 Static (Software-Timed) Digital Output Update
With static update, the software controls the rate and time of date, which is thus also
called software-timed update. Whenever the software sends a write command, the
state of digital output ports is updated as shown in Figure 3.27.
Figure 3.27 Static (software-timed) digital output update.
The advantage of state update is low latency. It is typically used for writing a single
value of digital output.
3.4.1.2 Buffered (Hardware-Timed) Digital Output Generation
With buffered generation, a hardware signal called sample clock controls the rate and
time of generation as shown in Figure 3.28. The sample clock can be generated
internally on the device or be provided externally. Refer to the device specifications
for supported sample clock sources and the maximum allowable frequency of sample
clock.
Figure 3.28 Buffered (hardware-timed) digital output generation.
The samples to be generated are provided by the application. They are first stored in
the buffer of the PC, moved to the onboard first-in-first-out (FIFO) memory of the
device by a direct memory access (DMA) engine, and placed on the digital output
channels one sample at a time. A buffer is a block of memory in the PC for temporar-
ily storing the data to be transferred to the onboard FIFO. Because the data is moved
in large blocks instead of one point at a time, buffered generation typically allow
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