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A.4
Digital Input
Channels
Sample rate
Sample clock source
Data buffer size
Input type
Input logic level
Input protection voltage
Pull-up resistor
Response time
Debounce filter
Edge detection
Pattern match detection
State latch
A.5
Digital Output
Channels
Update rate
Update clock source
Data buffer size
Output type
Output logic level
Load current
Response time
16 (2 ports)
1 MS/s max.
Internal or external
4,096 samples
5 V TTL
Logic high
2.0 V min.
Logic low
0.8 V max.
Working voltage
-0.25 V ~ 5.25 V
-0.5 V ~ 6.5 V
10 kΩ
25 ns max.
25 ns ~ 105 ms
Rising/falling/both edges
By port detection
Latch port state when interrupt occurs
16 (2 ports)
1 MS/s max.
Internal or external
4,096 samples
5 V TTL
Logic high
4.0 V min. @ 2 mA
Logic low
0.4 V max. @ 2 mA
One channel
8 mA max.
Per port summed
20 mA max.
25 ns max.
49
PCI-1716_Series User Manual
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