Advantech PCI-1716 User Manual page 6

3.2
3.3
3.4
3.5
PCI-1716_Series User Manual
3.1.3 Configuration for Buffered Analog Input Acquisition ................... 23
Figure 3.3 Post-trigger acquisition............................................. 24
Figure 3.4 Streaming acquisition. .............................................. 24
3.1.4 External Conversion Clock with Gate ......................................... 24
Figure 3.5 External conversion clock with gate. ........................ 24
Analog Output ......................................................................................... 25
3.2.1 Analog Output Resolution........................................................... 25
3.2.2 Analog Output Signal Glitch........................................................ 25
Figure 3.6 Power-on glitch remover of the analog output.......... 26
3.2.3 Output Status When Changing Range ....................................... 26
Figure 3.7 Output status when changing range......................... 26
3.2.4 Analog Output Data Generation Methods................................... 26
Figure 3.8 Static (software-timed) analog output update........... 27
Figure 3.9 Analog output asynchronous update. ...................... 27
Figure 3.10Analog output synchronous update.......................... 27
Figure 3.11Buffered (hardware-timed) analog output generation.
................................................................................. 28
3.2.5 Configuration for Buffered Analog Output Generation................ 28
Figure 3.12One-buffered generation. ......................................... 29
Figure 3.13One-buffered generation with delay. ........................ 29
Figure 3.14Streaming generation. .............................................. 29
Digital Input ............................................................................................. 30
3.3.1 Digital Input Acquisition Methods................................................ 30
Figure 3.15Instant (software-timed) digital input acquisition. ..... 30
Figure 3.16Buffered (hardware-timed) digital input acquisition. . 30
3.3.2 Configuration for Buffered Digital Input Acquisition .................... 31
Figure 3.17Post-trigger acquisition............................................. 31
Figure 3.18Streaming acquisition. .............................................. 31
3.3.3 Digital Input Interrupt .................................................................. 32
Figure 3.19Digital input interrupt at rising edges. ....................... 32
Figure 3.20Digital input interrupt at falling edges. ...................... 32
Figure 3.21Digital input interrupt at both edges.......................... 32
3.3.4 Digital Input Pattern Match Interrupt ........................................... 32
Figure 3.22Digital input pattern match interrupt for pattern
"10xx0100". .............................................................. 32
3.3.5 Digital Input Debounce Filter ...................................................... 33
Figure 3.23Digital input without debounce filter.......................... 33
Figure 3.24Digital input with debounce filter............................... 33
Figure 3.25Debounce filter sample clock. .................................. 34
3.3.6 Digital Input Status Latch............................................................ 34
Figure 3.26Digital input status latch. .......................................... 34
Digital Output .......................................................................................... 35
3.4.1 Digital Output Data Generation Methods.................................... 35
Figure 3.27Static (software-timed) digital output update. ........... 35
Figure 3.28Buffered (hardware-timed) digital output generation.35
3.4.2 Configuration for Buffered Digital Output Generation ................. 36
Figure 3.29One-buffered generation. ......................................... 36
Figure 3.30One-buffered generation with delay. ........................ 36
Figure 3.31Streaming generation. .............................................. 37
Counter ................................................................................................... 38
3.5.1 Event Counting ........................................................................... 38
Figure 3.32Rising edge event counting. ..................................... 38
Figure 3.33Falling edge event counting. .................................... 38
Figure 3.34Event counting with pause gate. .............................. 38
Figure 3.35Instant (software-timed) event counting. .................. 39
3.5.2 Frequency Measurement............................................................ 39
Figure 3.36Frequency measurement by period inversion. ......... 39
Figure 3.37Frequency measurement by counting number of pulses
in fixed duration. ....................................................... 40
3.5.3 One-Shot (Delayed Pulse Generation) ....................................... 40
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