Configuration For Buffered Analog Output Generation - Advantech PCI-1716 User Manual

3.2.4.2 Buffered (Hardware-Timed) Analog Output Generation
With buffered generation, a hardware signal called sample clock controls the rate and
time of generation as shown in Figure 3.11. The sample clock can be generated
internally on the device or be provided externally. Refer to the device specifications
for supported sample clock sources and the maximum allowable frequency of sample
clock.
Figure 3.11 Buffered (hardware-timed) analog output generation.
The samples to be generated are provided by the application. They are first stored in
the buffer of the PC, moved to the onboard first-in-first-out (FIFO) memory of the
device by a direct memory access (DMA) engine, and converted by the DAC one
sample at a time. A buffer is a block of memory in the PC for temporarily storing the
data to be transferred to the onboard FIFO. Because the data is moved in large
blocks instead of one point at a time, buffered generation typically allow much higher
transfer rates. Buffered generation is also called hardware-timed generation.\
The advantages of buffered generation over static update include:
The generation (update) rate can be much higher.

The time of sample is deterministic.

Hardware triggers can be used.

3.2.5

Configuration for Buffered Analog Output Generation

According to software configurations, buffered analog output generation can be clas-
sified into two types:
One-buffered analog output generation

Streaming analog output generation

3.2.5.1 One-Buffered Analog Output Generation
For one-buffered generation, only a specified number of samples is generated. The
generation starts when a start trigger is received and automatically stops when the
specified number of samples is generated. An example of 5-sample generation is
shown in Figure 3.12.
PCI-1716_Series User Manual 28