Timing Signals; Clock Signal; Synchronization - Advantech PCI-1716 User Manual

3.6

Timing Signals

3.6.1

Clock Signal

The clock signal can be generated internally or provided from external source. For
internal clock, when configuration is done, the clock frequency cannot be changed on
the fly during the acquisition or generation operation. For external clock, on the other
hand, clock frequency can be controlled by the external source in real time.
3.6.2

Synchronization

To synchronize the acquisition of multiple devices, all the devices must use the same
clock signal.
One of the devices is selected to be the master device, and others are slave devices.
The master device may generate clock signal internally, or accept them from external
source. It then routes this signal to the output terminal and sends it to all the slave
devices through external wirings for synchronized acquisition. To synchronize more
than two devices, both daisy-chain and star topology can be used as shown in Figure
3.43 and Figure 3.44, respectively. Star topology reduces intermediate signal delay
between devices. However, it also introduces signal degradation if too many loads
are present for one signal source. It is recommended to keep number of loads for one
signal source to be three or less.
Figure 3.43 Multiple devices synchronization with daisy-chain topology.
Figure 3.44 Multiple devices synchronization with star topology.
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