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Description of device limitations
1.
Wait until TXE flag is set before clearing TE bit
2.
Wait until TC flag is set before clearing TE bit
2.2
GPIO
2.2.1
Extra consumption on GPIOs PB0..1 on 20/25/28-pin devices
Description
For lower pin count devices, some GPIOs are not available on the package. The hardware
forces them to safe configuration.
In this situation the software reconfiguration of PB0..1 to analog mode opens a path
between V
observed if V
Workaround
Do not reconfigure PB0..1 to the analog mode when PB0..1 GPIOs are not available on the
device.
2.2.2
GPIOx locking mechanism not working properly for GPIOx_OTYPER
register
Description
Locking of GPIOx_OTYPER[i] with i = 15..8 depends from setting of GPIOx_LCKR[i-8] and
not from GPIOx_LCKR[i]. GPIOx_LCKR[i-8] is locking GPIOx_OTYPER[i] together with
GPIOx_OTYPER[i-8]. It is not possible to lock GPIOx_OTYPER[i] with i = 15...8, without
locking also GPIOx_OTYPER[i-8].
Workaround
The only way to lock GPIOx_OTYPER[i] with i=15..8 is to lock also GPIOx_OTYPER[i-8].
2.3
I2C
2.3.1
Wrong data sampling when data set-up time (t
one I2CCLK period
Description
The I²C-bus specification and user manual specify a minimum data set-up time (t
•
250 ns in Standard mode
•
100 ns in Fast mode
•
50 ns in Fast mode Plus
The I²C-bus SDA line is not correctly sampled when t
(I²C-bus peripheral clock) period: the previous SDA value is sampled instead of the current
one. This can result in a wrong receipt of slave address, data byte, or acknowledge bit.
8/21
and V
. Additional current consumption in the range of tens of µA can be
DDA
DDIOx
is higher than V
DDA
DocID026423 Rev 2
.
DDIOx
SU;DAT
STM32F038x6
) is shorter than
SU;DAT
SU;DAT
is smaller than one I2CCLK
) as:
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