10-Bit Master Mode: New Transfer Cannot Be Launched If First Part Of The Address Has Not Been Acknowledged By The Slave; Spi; Bsy Bit May Stay High When Spi Is Disabled - ST STM32F038 6 Series Errata Sheet

Description of device limitations
Workaround
Disable the I
2.3.8 10-bit master mode: new transfer cannot be launched if first part of the
address has not been acknowledged by the slave
Description
In master mode, the master automatically sends a STOP bit when the slave has not
acknowledged a byte during the address transmission.
In 10-bit addressing mode, if the first byte of the 10-bit address (5-bit header + 2 MSBs of
the address + direction bit) has not been acknowledged by the slave, the STOP bit is sent
but the START bit is not cleared and the master cannot launch a new transfer.
Workaround
When the I2C is configured in 10-bit addressing master mode and the NACKF status flag is
set in the I2C_ISR register while the START bit is still set in I2C_CR2 register, then proceed
as follows:
1. Wait for the STOP condition detection (STOPF = 1 in I2C_ISR register).
2. Disable the I2C peripheral.
3. Wait for a minimum of 3 APB cycles.
4. Enable the I2C peripheral again.
2.4

SPI

2.4.1

BSY bit may stay high when SPI is disabled

Description
The BSY flag may remain high upon disabling the SPI while operating in:
•
a master transmit mode and the TXE flag is low (data register full).
•
a master receive only mode (simplex receive or half-duplex bidirectional receive phase)
and an SCK strobing edge has not occurred since the transition of the RXNE flag from
low to high.
•
slave mode and NSS signal is removed during the communication.
Workaround
When the SPI operates in:
•
a master transmit mode, disable the SPI when TXE=1 and BSY=0.
•
a master receive only mode, ignore the BSY flag.
•
slave mode, do not remove the NSS signal during the communication.
12/21
2
C (PE=0) before entering Stop mode and re-enable it in Run mode.
DocID026423 Rev 2
STM32F038x6