Table Of Contents - ST STM32F038 6 Series Errata Sheet

Contents
Contents
1 Summary of device limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Description of device limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.6
2.1.7
2.2 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.1
2.2.2
2.3 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
2.3.8
2.4 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4.1
2/21
Start bit detected too soon when sampling for NACK signal from
the smartcard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Break request can prevent the Transmission Complete flag (TC)
from being set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
nRTS is active while RE or UE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Consistency not checked in mode 1 of automatic baud rate
detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Framing error (FE) flag low upon automatic baud rate detection error . . 7
Communication parameters reprogramming after ATR in Smartcard
mode when SCLK is used to clock the card . . . . . . . . . . . . . . . . . . . . . . 7
Last byte written in TDR might not be transmitted if TE is cleared
just after writing in TDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Extra consumption on GPIOs PB0..1 on 20/25/28-pin devices . . . . . . . . 8
GPIOx locking mechanism not working properly for GPIOx_OTYPER
register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Wrong data sampling when data set-up time (t
one I2CCLK period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Spurious bus error detection in master mode . . . . . . . . . . . . . . . . . . . . . 9
10-bit slave mode: wrong direction bit value after Read header
reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
10-bit combined with 7-bit slave mode: ADDCODE may indicate wrong
slave address detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Wakeup frames may not wakeup the MCU mode when STOP mode
2
entry follows I C enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Wakeup frame may not wakeup from STOP if t
HSI startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Wrong behavior in Stop mode when wakeup from Stop mode is
2
disabled in I C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
10-bit master mode: new transfer cannot be launched if first part of the
address has not been acknowledged by the slave 12
BSY bit may stay high when SPI is disabled . . . . . . . . . . . . . . . . . . . . . 12
DocID026423 Rev 2
STM32F038x6
) is shorter than
SU;DAT
is close to
HD;STA