10-Bit Combined With 7-Bit Slave Mode: Addcode May Indicate Wrong Slave Address Detection; Wakeup Frames May Not Wakeup The Mcu Mode When Stop Mode Entry Follows I 2 C Enabling - ST STM32F038 6 Series Errata Sheet

Description of device limitations
2.3.4 10-bit combined with 7-bit slave mode: ADDCODE may indicate wrong
slave address detection
Description
Under specific conditions, the ADDCODE (Address match code) in the I2C_ISR register
indicates a wrong slave address.
To see the limitation, all the following conditions have to be fulfilled:
•
The I
OA1MODE=1)
•
Another 7-bit slave address is enabled and the bits 1 to 7 of the 10-bit slave address
OA1 are equal to the 7-bit slave address, i.e., one of the configurations below is set:
–
–
–
–
–
–
–
–
–
–
–
–
• The master starts a transfer addressed to the 10-bit slave address OA1.
As a result, after the address reception, the ADDCODE value is OA1[7:1] equal to the 7-bit
slave address, instead of 0b11110 & OA1[9:8].
Workaround
None. If several slave addresses are enabled, mixing 10-bit and 7-bit addresses, the 10-bit
Slave address OA1 [7:1] must not be equal to the 7-bit slave address.
2.3.5 Wakeup frames may not wakeup the MCU mode when STOP mode
entry follows I
Description
2
If the I C is enabled (PE = 1) and wakeup from STOP enabled in I
transfer occurs on the I
SCL=0, the I
2
I C is addressed, it will not wake up the MCU and this address is not acknowledged.
Workaround
After enabling the I
to ensure that the eventual on-going frame is finished.
10/21
2
C slave address OA1 is enabled and configured in 10-bit mode (OA1EN=1 and
OA2EN=1 and OA2MSK = 0 and OA1[7:1] = OA2[7:1]
OA2EN=1 and OA2MSK = 1 and OA1[7:2] = OA2[7:2]
OA2EN=1 and OA2MSK = 2 and OA1[7:3] = OA2[7:3]
OA2EN=1 and OA2MSK = 3 and OA1[7:4] = OA2[7:4]
OA2EN=1 and OA2MSK = 4 and OA1[7:5] = OA2[7:5]
OA2EN=1 and OA2MSK = 5 and OA1[7:6] = OA2[7:6]
OA2EN=1 and OA2MSK = 6 and OA1[7] = OA2[7]
OA2EN=1 and OA2MSK = 7
GCEN=1 and OA1[7:1] = 0b0000000
ALERTEN=1 and OA1[7:1] = 0b0001100
SMBDEN=1 and OA1[7:1] = 0b1100001
SMBHEN=1 and OA1[7:1] = 0b0001000
2
C enabling
2
C bus and STOP mode is entered during the same transfer while
2
C is not able to detect the following START condition. This means that if the
2
C (PE is set to 1), wait for a temporization before entering STOP mode,
DocID026423 Rev 2
STM32F038x6
2
C (WUPEN=1) while a