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STM32F038x6
2.4.2
BSY bit may stay high at the end of a data transfer in slave mode
Description
In slave mode, The BSY bit is not reliable to handle the end of data frame transaction due to
some bad synchronization between the CPU clock and external SCK clock provided by the
SPI master. Sporadically, the BSY bit is not cleared at the end of a data frame transfer. As a
consequence, it is not recommended to rely on the BSY bit before entering low-power mode
or modifying the SPI configuration (e.g. direction of the bidirectional mode).
Workaround
•
When the SPI interface is in receive mode, the end of a transaction with the master can
be detected by the corresponding RXNE event when this flag is set after the last bit of
that transaction is sampled and the received data are stored.
•
When the following sequence is used, the synchronization issue does not occur. The
BSY bit works correctly and can be used to recognize the end of any transmission
transaction (including when RXNE is not raised in bidirectional mode):
a)
b)
c)
d)
Note:
The second workaround can be used only when the CPU is fast enough to disable the SPI
interface after a TXE event is detected while the data frame transfer is ongoing. It cannot be
implemented when the ratio between CPU and SPI clock is low and the data frame is
particularly short. At this specific case, the timeout can be measured from the TXE event
instead by calculating a fixed number of CPU clock cycles corresponding to the time
necessary to complete the data frame transaction.
2.4.3
Wrong CRC transmitted in master mode with delayed SCK feedback
Description
In transmit transaction of the SPI/I
CRC data transmission may be corrupted if the delay of an internal feedback signal derived
from the SCK output (further feedback clock) is greater than one APB clock period. While
data and CRC bit shifting and transfer is based on an internal clock, the CRC progressive
calculation uses the feedback clock. If the delay of the feedback clock is greater than one
APB period, the transmitted CRC value may get wrong.
The main factors contributing to the delay increase are low V
high SCK pin capacitive load and low SCK IO output speed. The SPI communication speed
has no impact.
Workaround
Set the application such as to speed up the SCK edges and / or slow down the APB clock,
through:
•
configuring the SCK output GPIO so as to reach lower output impedance
•
minimizing the capacitive load on the SCK output line
•
configuring the APB clock speed
Write the last data into data register.
Poll the TXE flag till it becomes high to make sure the data transfer has started.
Disable the SPI interface by clearing the SPE bit while the last data transfer is on
going.
Poll the BSY bit till it becomes low.
DocID026423 Rev 2
2
S interface in SPI master mode with CRC enabled, the
Description of device limitations
level, high temperature,
DD
13/21
18
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