Iwdg; Rvu, Pvu And Wvu Flags Are Not Reset In Stop Mode; Rvu, Pvu And Wvu Flags Are Not Reset With Low-Frequency Apb - ST STM32F038 6 Series Errata Sheet

Description of device limitations
2.7

IWDG

2.7.1

RVU, PVU and WVU flags are not reset in STOP mode

Description
The RVU,PVU and WVU flags of the IWDG_SR register are set by hardware after a write
access to the IWDG_RLR and the IWDG_PR registers, respectively. If the Stop mode is
entered immediately after the write access, the RVU,PVU and WVU flags are not reset by
hardware. Before performing a second write operation to the IWDG_RLR or the IWDG_PR
register, the application software must wait for the RVU, PVU and WVU flags to be reset.
However, since the RVU/PVU/WPU bit is not reset after exiting the Stop mode, the software
goes into an infinite loop and the independent watchdog (IWDG) generates a reset after the
programmed timeout period.
Workaround
Wait until the RVU, PVU and WVU flags of the IWDG_SR register are reset, before entering
the Stop mode.
2.7.2

RVU, PVU and WVU flags are not reset with low-frequency APB

Description
The RVU, PVU and WVU flags of the IWDG_SR register are set by hardware after a write
access to the IWDG_RLR and the IWDG_PR registers, respectively. If the APB clock
frequency is two times slower than the IWDG clock frequency, the RVU, PVU and WVU
flags will never be reset by hardware.
Workaround
None
18/21 DocID026423 Rev 2
STM32F038x6