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1. The REV_ID bits in the DBGMCU_IDCODE register indicate the revision code of the device (see the reference manual for details on the revision code). 2. Refer to datasheet for details on how to identify the silicon revision code on different types of package. October 2016 DocID026423 Rev 2 1/21 www.st.com...
Contents STM32F038x6 Contents Summary of device limitations ....... . 4 Description of device limitations .
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STM32F038x6 Contents 2.4.2 BSY bit may stay high at the end of a data transfer in slave mode ..13 2.4.3 Wrong CRC transmitted in master mode with delayed SCK feedback . 13 2.4.4 CRC error in SPI slave mode if internal NSS changes before CRC transfer .
Summary of device limitations STM32F038x6 Summary of device limitations The following table gives a quick references to all documented device limitations of STM32F038x6 and their status: A = workaround available N = no workaround available P = partial workaround available “-”...
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STM32F038x6 Summary of device limitations Table 3. Summary of device limitations (continued) Status Function Section Limitation Rev. ‘A’, ‘1’ 2.4.1 BSY bit may stay high when SPI is disabled 2.4.2 BSY bit may stay high at the end of a data transfer in slave mode 2.4.3 Wrong CRC transmitted in master mode with delayed SCK feedback 2.4.4...
Description of device limitations STM32F038x6 Description of device limitations The following sections describe device limitations and provide workarounds if available. They are grouped by device functions. USART 2.1.1 Start bit detected too soon when sampling for NACK signal from the smartcard Description In the ISO7816, when a character parity error is incorrect, the smartcard receiver shall transmit a NACK error signal at (10.5 +/- 0.2) etu after the character START bit falling edge.
STM32F038x6 Description of device limitations Workaround Configure the I/O used for nRTS as alternate function after setting the UE and RE bits. 2.1.4 Consistency not checked in mode 1 of automatic baud rate detection Description In mode 1 (ABRMOD = 01) of automatic baud rate detection, the Start bit then the first data bit duration is measured.
Description of device limitations STM32F038x6 Wait until TXE flag is set before clearing TE bit Wait until TC flag is set before clearing TE bit GPIO 2.2.1 Extra consumption on GPIOs PB0..1 on 20/25/28-pin devices Description For lower pin count devices, some GPIOs are not available on the package. The hardware forces them to safe configuration.
STM32F038x6 Description of device limitations Workaround Increase the I2CCLK frequency to get I2CCLK period within the transmitter minimum data set-up time. Alternatively, increase transmitter’s minimum data set-up time. 2.3.2 Spurious bus error detection in master mode Description In master mode, a bus error can be detected by mistake, so the BERR flag can be wrongly raised in the status register.
Description of device limitations STM32F038x6 2.3.4 10-bit combined with 7-bit slave mode: ADDCODE may indicate wrong slave address detection Description Under specific conditions, the ADDCODE (Address match code) in the I2C_ISR register indicates a wrong slave address. To see the limitation, all the following conditions have to be fulfilled: •...
STM32F038x6 Description of device limitations 2.3.6 Wakeup frame may not wakeup from STOP if t is close to HD;STA HSI startup time Description Under specific conditions and if the START condition hold time t duration is very close HD;STA to the HSI start-up time duration, the I C is not able to detect the address match and wake up the MCU from STOP.
Description of device limitations STM32F038x6 Workaround Disable the I C (PE=0) before entering Stop mode and re-enable it in Run mode. 2.3.8 10-bit master mode: new transfer cannot be launched if first part of the address has not been acknowledged by the slave Description In master mode, the master automatically sends a STOP bit when the slave has not acknowledged a byte during the address transmission.
STM32F038x6 Description of device limitations 2.4.2 BSY bit may stay high at the end of a data transfer in slave mode Description In slave mode, The BSY bit is not reliable to handle the end of data frame transaction due to some bad synchronization between the CPU clock and external SCK clock provided by the SPI master.
Description of device limitations STM32F038x6 2.4.4 CRC error in SPI slave mode if internal NSS changes before CRC transfer Description When the device is configured as SPI slave, the transition of the internal NSS after the CRCNEXT flag is set may result in wrong CRC value computed by the device and, as a consequence, a CRC error.
STM32F038x6 Description of device limitations Workaround The following measures can be adopted, jointly or individually: • Decrease the APB clock speed. • Configure the IO pad of the SCK pin to be faster. The following table gives the maximum allowable APB frequency versus GPIOx_OSPEEDR output speed control field setting for the SCK pin, at 30pF of capacitive load.
Description of device limitations STM32F038x6 2.4.8 In I S slave mode: WS level must be set by the external master when enabling the I2S Description In slave mode, the WS signal level is used only to start the communication. If the I2S (in slave mode) is enabled while the master is already sending the clock and the WS signal level is low (for I S protocol) or is high (for the LSB or MSB-justified mode), the slave starts...
STM32F038x6 Description of device limitations 2.5.3 RTC calendar registers are not locked properly Description When reading the calendar registers with BYPSHAD=0, the RTC_TR and RTC_DR registers may not be locked after the read of RTC_SSR register. This happens if the read of RTC_SSR is initiated one APB clock period before the shadow registers are updated.
Description of device limitations STM32F038x6 IWDG 2.7.1 RVU, PVU and WVU flags are not reset in STOP mode Description The RVU,PVU and WVU flags of the IWDG_SR register are set by hardware after a write access to the IWDG_RLR and the IWDG_PR registers, respectively. If the Stop mode is entered immediately after the write access, the RVU,PVU and WVU flags are not reset by hardware.
STM32F038x6 Revision history Revision history Table 5. Document revision history Date Revision Changes 12-Jun-2014 Initial release. Added: USART: – Section 2.1.1: Start bit detected too soon when sampling for NACK signal from the smartcard – Section 2.1.2: Break request can prevent the Transmission Complete flag (TC) from being set –...
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Revision history STM32F038x6 Table 5. Document revision history (continued) Date Revision Changes ADC: – Section 2.6.1: Overrun flag not set if EOC reset coincides with new conversion end – Section 2.6.2: ADEN bit cannot be set immediately after the ADC calibration IWDG: –...
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