Rtc Calendar Registers Are Not Locked Properly; Adc; Overrun Flag Not Set If Eoc Reset Coincides With New Conversion End; Aden Bit Cannot Be Set Immediately After The Adc Calibration - ST STM32F038 6 Series Errata Sheet

STM32F038x6
2.5.3

RTC calendar registers are not locked properly

Description
When reading the calendar registers with BYPSHAD=0, the RTC_TR and RTC_DR
registers may not be locked after the read of RTC_SSR register. This happens if the read of
RTC_SSR is initiated one APB clock period before the shadow registers are updated. This
can result in a non-consistency of the 3 registers. Similarly, RTC_DR register can be
updated after the read of the RTC_TR register instead of being locked.
Workaround
1. Use BYPSHAD = 1 mode (Bypass shadow registers), or
2. In case BYPSHAD = 0: read SSR again after reading SSR/TR/DR to confirm that SSR
is still the same, otherwise read the values again.
2.6

ADC

2.6.1

Overrun flag not set if EOC reset coincides with new conversion end

Description
If the EOC flag is cleared by ADC_DR register read operation or by software during the
same APB cycle in which the data from a new conversion are written in the ADC_DR
register, the overrun event duly occurs (which results in the loss of either current or new
data) but the overrun flag (OVR) may stay low.
Workaround
Clear the EOC flag through ADC_DR register read operation or by software within less than
one ADC conversion cycle period from the last conversion cycle end, so as to avoid the
coincidence with the new conversion cycle end.
2.6.2

ADEN bit cannot be set immediately after the ADC calibration

Description
At the end of the ADC calibration, an internal reset of ADEN bit occurs four ADC clock
cycles after the ADCAL bit is cleared by hardware. As a consequence, if the ADEN bit is set
within those four ADC clock cycles, it is reset shortly after by the calibration logic and the
ADC remains disabled.
Workaround
1. Keep setting the ADEN bit until the ADRDY flag goes high.
2. After the ADCAL is cleared, wait for a minimum of four ADC clock cycles before setting
the ADEN bit.
DocID026423 Rev 2
Description of device limitations
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