Packing Mode Limitation At Reception - ST STM32F038 6 Series Errata Sheet

STM32F038x6
Workaround
The following measures can be adopted, jointly or individually:
•
Decrease the APB clock speed.
•
Configure the IO pad of the SCK pin to be faster.
The following table gives the maximum allowable APB frequency versus GPIOx_OSPEEDR
output speed control field setting for the SCK pin, at 30pF of capacitive load.
OSPEEDR [1:0]
2.4.7

Packing mode limitation at reception

Description
When the SPI is configured in the short data frame mode, the packing mode on the
reception side may not be usable. Using this feature may generate a wrong RXNE event to
an Interrupt or DMA request and so the software may read back inconsistent data with FIFO
pointers misalignment on the reception FIFO.
If the packing mode is used in reception mode, the FIFO reception threshold has to be set to
16 bits. Under those setting and conditions, when a read operation (half-word to read two
data in one APB access) takes place while the FIFO level is equal to 3/4 (new data came
before the two first ones are read), the 16-bit read decreases the FIFO level to 1/4. The
RXNE flag is not de-asserted and a new request is present to read back next two packed
data although the FIFO contains half of them only. Read and write pointers in the FIFO
become misaligned and the data is corrupted.
The worst case is the SPI slave and SPI master running in continuous mode without clock
interruption between data transfers.
In full duplex Master mode, the packing runs correctly if the SPI is working in non-
continuous mode, meaning that the SPI always transfers even number of data under 16-bit
Rx FIFO threshold, then stops the data transmission until all the data received are read back
before sending the next data. Such safe read can't be fully guaranteed if SCK signal is
continuous especially when receiver can't guarantee to exclude any 16-bit access to FIFO
when it is just ¾ occupied.
Workaround
There is no workaround in any continuous receive mode.
The only way to avoid this data corruption would be to slow down the SPI communication
clock frequency in order to provide a sufficient time to the DMA (best case) or software to
read back data in time to prevent any 16-bit FIFO reading at its critical ¾ occupancy.
Table 4. Maximum allowable APB frequency at 30pF load
for SCK pin
11 (high)
01 (medium)
x0 (low)
DocID026423 Rev 2
Description of device limitations
Max. APB frequency
for SPI mode
[MHz]
48
36
28
Max. APB frequency
2
for I S mode
[MHz]
48
36
20
15/21
18