Crc Error In Spi Slave Mode If Internal Nss Changes Before Crc; Transfer; Spi Crc Corrupted Upon Dma Transaction Completion By Another; Peripheral - ST STM32F038 6 Series Errata Sheet

Description of device limitations
2.4.4

CRC error in SPI slave mode if internal NSS changes before CRC

transfer

Description
When the device is configured as SPI slave, the transition of the internal NSS after the
CRCNEXT flag is set may result in wrong CRC value computed by the device and, as a
consequence, a CRC error. As a consequence, the NSS pulse mode cannot be used along
with the CRC function.
Workaround
Prevent the internal NSS signal from changing in the critical period, by configuring the
device to software NSS control if the SPI master pulses the NSS (for example in NSS pulse
mode).
2.4.5

SPI CRC corrupted upon DMA transaction completion by another

peripheral

Description
When the following conditions are all met:
•
CRC function for the SPI is enabled,
•
SPI transaction managed by software (as opposed to DMA) is ongoing and CRCNEXT
flag set,
•
another peripheral using the same DMA channel on which the SPI is mapped
completes a DMA transfer,
the CRCNEXT bit is unexpectedly cleared and the SPI CRC calculation may be corrupted,
setting the CRC error flag.
Workaround
If possible, do not use the DMA channel, on which the SPI is mapped, by any other
peripheral.
2.4.6 Corrupted last bit of data and/or CRC, received in master mode with
delayed SCK feedback
Description
In receive transaction, in both I
is not captured when signal provided by internal feedback loop from the SCK pin exceeds a
critical delay. The lastly transacted bit of the stored data then keeps value from the pattern
received previously. As a consequence, the last receive data bit may be wrong and/or the
CRCERR flag can be unduly asserted in the SPI mode if any data under check sum and/or
just the CRC pattern is wrongly captured. At lower APB frequencies, the I
sensitive than the SPI mode, especially when odd factor of the I2S prescaler is set.
The main factors contributing to the delay increase are low V
high SCK pin capacitive load and low SCK IO output speed. The SPI communication speed
has no impact.
14/21
2
S and SPI master modes, the last bit of the transacted frame
DocID026423 Rev 2
STM32F038x6
2
S mode is more
level, high temperature,
DD