Table of Contents
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37
B66_L18_N
39
B66_L18_P
41
GND
43
B25_L4_N
45
B25_L4_P
47
GND
49
B26_L11_P
51
B26_L11_N
53
GND
55
B26_L10_N
57
B26_L10_P
59
GND
61
B26_L7_N
63
B26_L7_P
65
GND
67
B26_L9_N
69
B26_L9_P
71
GND
73
B26_L5_N
79
B26_L5_P
77
GND
79
B26_L1_P
81
B26_L1_N
83
GND
85
505_CLK2_P
87
505_CLK2_P
89
GND
91
505_CLK0_P
93
505_CLK0_N
95
GND
97
505_TX3_P
99
505_TX3_N
101
GND
103
505_RX3_P
105
505_RX3_N
107
GND
29 / 33
ZYNQ Ultrascale + FPGA Board ACU3EG User Manual
D9
E9
-
H12
J12
-
K14
J14
-
H13
H14
-
F13
G13
-
G14
G15
-
D14
D15
-
B15
A15
-
C21
C22
-
F23
F24
-
B23
B24
-
A25
A26
-
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38
B25_L12_P
40
B25_L12_N
42
GND
44
B25_L11_P
46
B25_L11_N
48
GND
50
B25_L6_N
52
B25_L6_P
54
GND
56
B26_L6_N
58
B26_L6_P
60
GND
62
B26_L3_N
64
B26_L3_P
66
GND
68
B26_L2_N
70
B26_L2_P
72
GND
74
B26_L4_N
76
B26_L4_P
78
GND
80
B26_L12_P
82
B26_L12_N
84
GND
86
505_CLK1_P
88
505_CLK1_P
90
GND
92
505_CLK3_P
94
505_CLK3_N
96
GND
98
505_TX1_P
100
505_TX1_N
102
GND
104
505_TX0_P
106
505_TX0_N
108
GND
D12
C12
-
A12
A11
-
F11
F12
-
E13
E14
-
A13
B13
-
A14
B14
-
C13
C14
-
L14
L13
-
E21
E22
-
A21
A22
-
D23
D24
-
E25
E26
-
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