Alinx ACU3EG User Manual page 10

PS Side DDR4 DRAM pin assignment:
Signal Name
PS_DDR4_DQS0_P
PS_DDR4_DQS0_N
PS_DDR4_DQS1_P
PS_DDR4_DQS1_N
PS_DDR4_DQS2_P
PS_DDR4_DQS2_N
PS_DDR4_DQS3_P
PS_DDR4_DQS3_N
PS_DDR4_DQS4_P
PS_DDR4_DQS4_N
PS_DDR4_DQS5_P
PS_DDR4_DQS5_N
PS_DDR4_DQS6_P
PS_DDR4_DQS6_N
PS_DDR4_DQS7_P
PS_DDR4_DQS7_N
PS_DDR4_DQ0
PS_DDR4_DQ1
PS_DDR4_DQ2
PS_DDR4_DQ3
PS_DDR4_DQ4
PS_DDR4_DQ5
PS_DDR4_DQ6
PS_DDR4_DQ7
PS_DDR4_DQ8
PS_DDR4_DQ9
PS_DDR4_DQ10
PS_DDR4_DQ11
PS_DDR4_DQ12
PS_DDR4_DQ13
PS_DDR4_DQ14
PS_DDR4_DQ15
PS_DDR4_DQ16
PS_DDR4_DQ17
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ZYNQ Ultrascale + FPGA Board ACU3EG User Manual
Pin Name
PS_DDR_DQS_P0_504
PS_DDR_DQS_N0_504
PS_DDR_DQS_P1_504
PS_DDR_DQS_N1_504
PS_DDR_DQS_P2_504
PS_DDR_DQS_N2_504
PS_DDR_DQS_P3_504
PS_DDR_DQS_N3_504
PS_DDR_DQS_P4_504
PS_DDR_DQS_N4_504
PS_DDR_DQS_P5_504
PS_DDR_DQS_N5_504
PS_DDR_DQS_P6_504
PS_DDR_DQS_N6_504
PS_DDR_DQS_P7_504
PS_DDR_DQS_N7_504
PS_DDR_DQ0_504
PS_DDR_DQ1_504
PS_DDR_DQ2_504
PS_DDR_DQ3_504
PS_DDR_DQ4_504
PS_DDR_DQ5_504
PS_DDR_DQ6_504
PS_DDR_DQ7_504
PS_DDR_DQ8_504
PS_DDR_DQ9_504
PS_DDR_DQ10_504
PS_DDR_DQ11_504
PS_DDR_DQ12_504
PS_DDR_DQ13_504
PS_DDR_DQ14_504
PS_DDR_DQ15_504
PS_DDR_DQ16_504
PS_DDR_DQ17_504
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Pin Number
AF21
AG21
AF23
AG23
AF25
AF26
AE27
AF27
N23
M23
L23
K23
N26
N27
J26
J27
AD21
AE20
AD20
AF20
AH21
AH20
AH19
AG19
AF22
AH22
AE22
AD22
AH23
AH24
AE24
AG24
AC26
AD26