Alinx ACU3EG User Manual page 13

PS_DDR4_ALERT_B
PS_DDR4_BA0
PS_DDR4_BA1
PS_DDR4_BG0
PS_DDR4_CS0_B
PS_DDR4_ODT0
PS_DDR4_PARITY
PS_DDR4_RESET_B
PS_DDR4_CLK0_P
PS_DDR4_CLK0_N
PS_DDR4_CKE0
PL Side DDR4 DRAM pin assignment:
Signal Name
PL_DDR4_DQS0_P
PL_DDR4_DQS0_N
PL_DDR4_DQS1_P
PL_DDR4_DQS1_N
PL_DDR4_DQ0
PL_DDR4_DQ1
PL_DDR4_DQ2
PL_DDR4_DQ3
PL_DDR4_DQ4
PL_DDR4_DQ5
PL_DDR4_DQ6
PL_DDR4_DQ7
PL_DDR4_DQ8
PL_DDR4_DQ9
PL_DDR4_DQ10
PL_DDR4_DQ11
PL_DDR4_DQ12
PL_DDR4_DQ13
PL_DDR4_DQ14
PL_DDR4_DQ15
PL_DDR4_DM0
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ZYNQ Ultrascale + FPGA Board ACU3EG User Manual
PS_DDR_ALERT_N_504
PS_DDR_BA0_504
PS_DDR_BA1_504
PS_DDR_BG0_504
PS_DDR_CS_N0_504
PS_DDR_ODT0_504
PS_DDR_PARITY_504
PS_DDR_RST_N_504
PS_DDR_CK0_P_504
PS_DDR_CK0_N_504
PS_DDR_CKE0_504
Pin Name
IO_L22P_T3U_N6_DBC_AD0P_64
IO_L22N_T3U_N7_DBC_AD0N_64
IO_L16P_T2U_N6_QBC_AD3P_64
IO_L16N_T2U_N7_QBC_AD3N_64
IO_L24N_T3U_N11_64
IO_L24P_T3U_N10_64
IO_L23N_T3U_N9_64
IO_L23P_T3U_N8_64
IO_L21N_T3L_N5_AD8N_64
IO_L21P_T3L_N4_AD8P_64
IO_L20N_T3L_N3_AD1N_64
IO_L20P_T3L_N2_AD1P_64
IO_L18N_T2U_N11_AD2N_64
IO_L18P_T2U_N10_AD2P_64
IO_L17N_T2U_N9_AD10N_64
IO_L17P_T2U_N8_AD10P_64
IO_L15N_T2L_N5_AD11N_64
IO_L15P_T2L_N4_AD11P_64
IO_L14N_T2L_N3_GC_64
IO_L14P_T2L_N2_GC_64
IO_L19P_T3L_N0_DBC_AD9P_64
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U25
V23
W22
W24
W27
U28
V24
U23
W25
W26
V28
Pin Number
AE2
AF2
AD2
AD1
AG1
AF1
AH1
AH2
AF3
AE3
AH3
AG3
AC1
AB1
AC2
AB2
AB3
AB4
AC3
AC4
AG4