Alinx ACU3EG User Manual
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Alinx ACU3EG User Manual

Zynq ultrascale+ fpga development board
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ZYNQ UltraScale+
FPGA Development Board
AXU3EG
User Manual

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Summary of Contents for Alinx ACU3EG

  • Page 1 ZYNQ UltraScale+ FPGA Development Board AXU3EG User Manual...

  • Page 2: Version Record

    Rev 1.2 2022-04-30 Rachel Zhou The English version was translated by Shanghai Tianhui Trading Company. They has not been officially Review by ALINX and are for reference only. If there are any errors, please send email to rachel.zhou@aithtech.com for correction.

  • Page 3: Table Of Contents

    ZYNQ Ultrascale + FPGA Core Board ACU3EG User Manual Table of Contents Version Record .....................2 Part 1: ACU3EG core board Introduction ............ 4 Part 2: ZYNQ Chip ..................5 Part 3: DDR4 DRAM ..................7 Part 4: QSPI Flash ..................14 Part 5: eMMC Flash ...................

  • Page 4: Part 1: Acu3Eg Core Board Introduction

    ZYNQ Ultrascale + FPGA Core Board ACU3EG User Manual Part 1: ACU3EG core board Introduction ACU3EG (core board model, the same below) FPGA core board, ZYNQ chip is based on XCZU3EG-1SFVC784I of XILINX company Zynq UltraScale+ MPSoCs EG series. This core board uses 5 Micron DDR4 chips MT40A512M16GE, of which 4 DDR4 chips are mounted on the PS side to form a 64-bit data bus bandwidth and 4GB capacity.

  • Page 5: Part 2: Zynq Chip

    Figure 1-1: ACU3EG Core Board (Front View) Part 2: ZYNQ Chip The FPGA core board ACU3Eg uses Xilinx's Zynq UltraScale+ MPSoCs EG series chip, module XCZU3EG-1SFVC784I. The PS system of the ZU3EG chip integrates 4 ARM Cortex™-A53 processors with a speed of up to 1.2Ghz and supports Level 2 Cache;...
  • Page 6 ZYNQ Ultrascale + FPGA Core Board ACU3EG User Manual Figure 2-1: Overall Block Diagram of the ZYNQ ZU3EG Chip The main parameters of the PS system part are as follows:  ARM quad-core Cortex ™ -A53 processor, speed up to 1.2GHz, each...

  • Page 7: Part 3: Ddr4 Dram

    SFVC784 Part 3: DDR4 DRAM The ACU3EG core board is equipped with 5 Micron (Micron) 1GB DDR4 chips, model MT40A512M16LY-062E, of which 4 DDR4 chips are mounted on the PS side to form a 64-bit data bus bandwidth and 4GB capacity. One DDR4 chip is mounted on the PL end, which is a 16-bit data bus width and a capacity of 1GB.
  • Page 8 ZYNQ Ultrascale + FPGA Core Board ACU3EG User Manual can reach 1200MHz (data rate 2400Mbps), and the 4 DDR4 storage systems are directly connected to the memory interface of the PS BANK504. The highest operating speed of the DDR4 SDRAM on the PL side can reach 1066MHz (data rate 2133Mbps), and a piece of DDR4 is connected to the BANK64 interface of the FPGA.
  • Page 9 ZYNQ Ultrascale + FPGA Core Board ACU3EG User Manual The hardware connection of DDR4 SDRAM on the Pl Side is shown in Figure 3-2: Figure 3-2: DDR3 DRAM schematic diagram PS Side DDR4 DRAM pin assignment: Signal Name Pin Name...
  • Page 10 ZYNQ Ultrascale + FPGA Core Board ACU3EG User Manual PS_DDR4_DQS6_N PS_DDR_DQS_N6_504 PS_DDR4_DQS7_P PS_DDR_DQS_P7_504 PS_DDR4_DQS7_N PS_DDR_DQS_N7_504 PS_DDR4_DQ0 PS_DDR_DQ0_504 AD21 PS_DDR4_DQ1 PS_DDR_DQ1_504 AE20 PS_DDR4_DQ2 PS_DDR_DQ2_504 AD20 PS_DDR4_DQ3 PS_DDR_DQ3_504 AF20 PS_DDR4_DQ4 PS_DDR_DQ4_504 AH21 PS_DDR4_DQ5 PS_DDR_DQ5_504 AH20 PS_DDR4_DQ6 PS_DDR_DQ6_504 AH19 PS_DDR4_DQ7 PS_DDR_DQ7_504 AG19 PS_DDR4_DQ8...
  • Page 11 ZYNQ Ultrascale + FPGA Core Board ACU3EG User Manual PS_DDR4_DQ33 PS_DDR_DQ33_504 PS_DDR4_DQ34 PS_DDR_DQ34_504 PS_DDR4_DQ35 PS_DDR_DQ35_504 PS_DDR4_DQ36 PS_DDR_DQ36_504 PS_DDR4_DQ37 PS_DDR_DQ37_504 PS_DDR4_DQ38 PS_DDR_DQ38_504 PS_DDR4_DQ39 PS_DDR_DQ39_504 PS_DDR4_DQ40 PS_DDR_DQ40_504 PS_DDR4_DQ41 PS_DDR_DQ41_504 PS_DDR4_DQ42 PS_DDR_DQ42_504 PS_DDR4_DQ43 PS_DDR_DQ43_504 PS_DDR4_DQ44 PS_DDR_DQ44_504 PS_DDR4_DQ45 PS_DDR_DQ45_504 PS_DDR4_DQ46 PS_DDR_DQ46_504 PS_DDR4_DQ47 PS_DDR_DQ47_504 PS_DDR4_DQ48...
  • Page 12 ZYNQ Ultrascale + FPGA Core Board ACU3EG User Manual PS_DDR4_DM5 PS_DDR_DM5_504 PS_DDR4_DM6 PS_DDR_DM6_504 PS_DDR4_DM7 PS_DDR_DM7_504 PS_DDR4_A0 PS_DDR_A0_504 PS_DDR4_A1 PS_DDR_A1_504 PS_DDR4_A2 PS_DDR_A2_504 AB28 PS_DDR4_A3 PS_DDR_A3_504 AA28 PS_DDR4_A4 PS_DDR_A4_504 PS_DDR4_A5 PS_DDR_A5_504 AA27 PS_DDR4_A6 PS_DDR_A6_504 PS_DDR4_A7 PS_DDR_A7_504 AA23 PS_DDR4_A8 PS_DDR_A8_504 AA22 PS_DDR4_A9 PS_DDR_A9_504...
  • Page 13 ZYNQ Ultrascale + FPGA Core Board ACU3EG User Manual PL_DDR4_DQS0_P IO_L22P_T3U_N6_DBC_AD0P_64 PL_DDR4_DQS0_N IO_L22N_T3U_N7_DBC_AD0N_64 PL_DDR4_DQS1_P IO_L16P_T2U_N6_QBC_AD3P_64 PL_DDR4_DQS1_N IO_L16N_T2U_N7_QBC_AD3N_64 PL_DDR4_DQ0 IO_L24N_T3U_N11_64 PL_DDR4_DQ1 IO_L24P_T3U_N10_64 PL_DDR4_DQ2 IO_L23N_T3U_N9_64 PL_DDR4_DQ3 IO_L23P_T3U_N8_64 PL_DDR4_DQ4 IO_L21N_T3L_N5_AD8N_64 PL_DDR4_DQ5 IO_L21P_T3L_N4_AD8P_64 PL_DDR4_DQ6 IO_L20N_T3L_N3_AD1N_64 PL_DDR4_DQ7 IO_L20P_T3L_N2_AD1P_64 PL_DDR4_DQ8 IO_L18N_T2U_N11_AD2N_64 PL_DDR4_DQ9 IO_L18P_T2U_N10_AD2P_64 PL_DDR4_DQ10 IO_L17N_T2U_N9_AD10N_64 PL_DDR4_DQ11...

  • Page 14: Part 4: Qspi Flash

    PL_DDR4_OTD IO_L19N_T3L_N1_DBC_AD9N_64 Part 4: QSPI Flash The FPGA core board ACU3EG is equipped with one 256MBit Quad-SPI FLASH chip to form an 8-bit bandwidth data bus, the flash model is MT25QU256ABA1EW9, which uses the 1.8V CMOS voltage standard. Due to the non-volatile nature of QSPI FLASH, it can be used as a boot device for the system to store the boot image of the system.

  • Page 15: Part 5: Emmc Flash

    PS_MIO5_500 AD16 Part 5: eMMC Flash The ACU3EG core board is equipped with a large-capacity 8GB eMMC FLASH chip, the model is MTFC8GAKAJCN-4M, it supports the HS-MMC interface of the JEDEC e-MMC V5.0 standard, and the level supports 1.8V or 3.3V.
  • Page 16 ZYNQ Ultrascale + FPGA Core Board ACU3EG User Manual The eMMC FLASH is connected to the GPIO port of the BANK500 of the PS part of the ZYNQ UltraScale+. In the system design, it is necessary to configure the GPIO port function of the PS side as an EMMC interface. Figure 5-1 shows the part of eMMC Flash in the schematic diagram.

  • Page 17: Part 6: Clock Configuration

    ZYNQ Ultrascale + FPGA Core Board ACU3EG User Manual Part 6: Clock configuration The core board provides reference clock and RTC real-time clock for PS system and PL logic respectively, so that PS system and PL logic can work independently. The schematic diagram of the clock circuit design is shown in...
  • Page 18 ZYNQ Ultrascale + FPGA Core Board ACU3EG User Manual Clock pin assignment: Signal Name PS_PADI_503 PS_PADO_503 PS System Clock Source The X1 crystal on the core board provides a 33.333MHz clock input for the PS part. The clock input is connected to the PS_REF_CLK_503 pin of BANK503 of the ZYNQ chip.

  • Page 19: Part 7: Led

    Part 7: LED There is a red power indicator (PWR) and a configuration LED (DONE) on the ACU3EG core board. When the core board is powered on, the power indicator will light up; after the FPGA configuration program, the configuration LED light will light up.

  • Page 20: Part 8: Power Supply

    ZYNQ Ultrascale + FPGA Core Board ACU3EG User Manual Part 8: Power Supply The power supply voltage of the ACU3EG core board is DC12V, which is supplied by connecting the carrier board. The core board uses a PMIC chip TPS6508641 to generate all the power required by the XCZU3EG chip. For the TPS6508641 power supply design, please refer to the power supply chip manual.

  • Page 21: Part 9: Acu3Eg Core Board Form Factors

    ZYNQ Ultrascale + FPGA Core Board ACU3EG User Manual In addition, the VCCIO power supply of BANK65 and BANK66 of XCZU3EG chip is provided by the carrier board, which is convenient for users to modify, but the maximum power supply cannot exceed 1.8V.
  • Page 22 ZYNQ Ultrascale + FPGA Core Board ACU3EG User Manual The connectors used is Panasonic AXK5A2137YG, and the corresponding connector model in the carrier board is Panasonic AXK6A2337YG. Among them, J29 is connected to the IO of BANK65 and BANK66, J30 is connectted to...
  • Page 23 ZYNQ Ultrascale + FPGA Core Board ACU3EG User Manual B65_L14_P B65_L19_P B65_L14_N B65_L19_N B65_L5_N B65_L18_P B65_L5_P B65_L18_N B65_L11_N B65_L8_P B65_L11_P B65_L8_N B65_L10_N B65_L24_N B65_L10_P B65_L24_P B66_L3_P B65_L12_P B66_L3_N B65_L12_N B66_L1_P B65_L13_N B66_L1_N B65_L13_P B66_L6_P B65_L21_P B66_L6_N B65_L21_N B66_L16_P B65_L23_P B66_L16_N...
  • Page 24 ZYNQ Ultrascale + FPGA Core Board ACU3EG User Manual B66_L13_N B66_L10_P B66_L13_P B66_L10_N B66_L8_N B66_L9_P B66_L8_P B66_L9_N Pin assignment of board to board connector J30 J30 Pin Signal Name J30 Pin Signal Name Number Number B66_L14_P FPGA_TDI B66_L14_N FPGA_TCK B66_L22_P...
  • Page 25 ZYNQ Ultrascale + FPGA Core Board ACU3EG User Manual B26_L11_N B25_L6_P B26_L10_N B26_L6_N B26_L10_P B26_L6_P B26_L7_N B26_L3_N B26_L7_P B26_L3_P B26_L9_N B26_L2_N B26_L9_P B26_L2_P B26_L5_N B26_L4_N B26_L5_P B26_L4_P B26_L1_P B26_L12_P B26_L1_N B26_L12_N 505_CLK2_P 505_CLK1_P 505_CLK2_P 505_CLK1_P 505_CLK0_P 505_CLK3_P 505_CLK0_N 505_CLK3_N 505_TX3_P...
  • Page 26 ZYNQ Ultrascale + FPGA Core Board ACU3EG User Manual Pin assignment of board to board connector J31 J31 Pin Signal Name J31 Pin Signal Name Pin Number Number B24_L10_P B24_L7_P AA13 B24_L10_N B24_L7_N AB13 B24_L6_P AC14 B44_L6_P AC12 B24_L6_N AC13...
  • Page 27 ZYNQ Ultrascale + FPGA Core Board ACU3EG User Manual B44_L2_N AG11 B44_L4_N AF10 B44_L2_P AF11 B44_L4_P AE10 VBAT_IN B44_L11_P B44_L11_N PS_POR_B 224_CLK0_P 224_CLK1_P 224_CLK0_N 224_CLK1_N 224_RX3_P 224_TX3_P 224_RX3_N 224_TX3_N 224_RX2_P 224_TX2_P 224_RX2_N 224_TX2_N 224_RX1_P 224_TX1_P 224_RX1_N 224_TX1_N 224_RX0_P 224_TX0_P 224_RX0_N...
  • Page 28 ZYNQ Ultrascale + FPGA Core Board ACU3EG User Manual PS_MODE0 PS_MIO52 PS_MODE1 PS_MIO55 PS_MODE2 PS_MIO56 PS_MODE3 PS_MIO57 PS_MIO36 PS_MIO54 PS_MIO37 PS_MIO27 PS_MIO28 PS_MIO77 PS_MIO59 PS_MIO76 PS_MIO60 PS_MIO61 PS_MIO39 PS_MIO62 PS_MIO38 PS_MIO63 PS_MIO65 PS_MIO40 PS_MIO66 PS_MIO44 PS_MIO67 PS_MIO45 PS_MIO68 PS_MIO47 PS_MIO64...
  • Page 29 ZYNQ Ultrascale + FPGA Core Board ACU3EG User Manual PS_MIO26 PS_MIO43 PS_MIO24 AB19 PS_MIO51 PS_MIO25 AB21 PS_MIO42 PS_MIO33 VCCO_65 VCCO_66 VCCO_65 VCCO_66 VCCO_65 VCCO_66 +12V +12V +12V +12V +12V +12V +12V +12V +12V +12V +12V +12V +12V +12V Amazon Store: https://www.amazon.com/alinx...

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