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6 I/O PORTS (PPORT)
Note: When enabling the key-entry reset function, be sure to configure the port pins to be used for it
as general-purpose input pins before setting the PCLK.KRSTCFG[1:0] bits.
PPORT issues a reset request immediately after all the input pins specified by the PCLK.KRSTCFG[1:0] are
set to a low level if the chattering filter function is disabled (initial status). To issue a reset request only when
low-level signals longer than the time configured are input, enable the chattering filter function for all the ports
used for key-entry reset.
The pins configured for key-entry reset can also be used as general-purpose input pins.
6.5 Interrupts
When the GPIO function is selected for the port with an interrupt function, the port input interrupt function can be
used.
Interrupt
Port input interrupt
PxINTF.PxIFy
PINTFGRP.PxINT
Interrupt edge selection
Port input interrupts will occur at the falling edge of the input signal when setting the PxINTCTL.PxEDGEy bit
to 1, or the rising edge when setting to 0.
Interrupt enable
PPORT provides interrupt enable bits (PxINTCTL.PxIEy bit) corresponding to each interrupt flag. An inter-
rupt request is sent to the interrupt controller only when the interrupt flag, of which interrupt has been enabled
by the interrupt enable bit, is set. For more information on interrupt control, refer to the "Interrupt Controller"
chapter.
Interrupt check in port group unit
When interrupts are enabled in two or more port groups, check the PINTFGRP.PxINT bit in the interrupt han-
dler first. It helps minimize the handler codes for finding the port that has generated an interrupt. If this bit is
set to 1, an interrupt has occurred in the port group. Next, check the PxINTF.PxIFy bit set to 1 in the port group
to determine the port that has generated an interrupt. Clearing the PxINTF.PxIFy bit also clears the PINTFGRP.
PxINT bit. If the port is set to interrupt disabled status by the PxINTCTL.PxIEy bit, the PINTFGRP.PxINT bit
will not be set even if the PxINTF.PxIFy bit is set to 1.
6.6 Control Registers
This section describes the same control registers of all port groups as a single register. For the register and bit con-
figurations in each port group and their initial values, refer to "Control Register and Port Function Configuration of
this IC."
Px Port Data Register
Register name
Bit
PxDAT
15–8 PxOUT[7:0]
7–0 PxIN[7:0]
*1: This register is effective when the GPIO function is selected.
*2: The bit configuration differs depending on the port group.
*3: The initial value may be changed by the port.
Bits 15–8 PxOUT[7:0]
These bits are used to set data to be output from the GPIO port pins.
1 (R/W): Output high level from the port pin
0 (R/W): Output low level from the port pin
6-6
Table 6.5.1 Port Input Interrupt Function
Interrupt flag
Rising or falling edge of the input signal
Setting an interrupt flag in the port group
Bit name
Initial
0x00
0x00
Seiko Epson Corporation
Set condition
Reset
R/W
H0
R/W
–
H0
R
S1C17W14/W16 TECHNICAL MANUAL
Clear condition
Writing 1
Clearing PxINTF.PxIFy
Remarks
(Rev. 1.2)
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