Epson S1C17W14 Technical Manual page 22

S1C17W16
Port function
or signal
assignment Pad name
SEG46 SEG46
82
SEG45 SEG45
83
SEG44 SEG44 84
SEG43 SEG43
85
SEG42 SEG42 86
SEG41 SEG41
87
SEG40 SEG40
88
SEG39 SEG39
89
SEG38 SEG38
90
SEG37 SEG37
91
SEG36 SEG36
92
SEG35 SEG35
93
SEG34 SEG34
94
SEG33 SEG33
95
SEG32 SEG32
96
SEG31 SEG31 97
SEG30 SEG30
98
SEG29 SEG29 99
SEG28 SEG28
100
SEG27 SEG27
101
SEG26 SEG26
102
SEG25 SEG25
103
SEG24 SEG24
104
SEG23 SEG23
105
V V
106
DD DD
C C
107
P1 P1
C C
108
P2 P2
Pad opening No. 1–28, 55–81:
No. 29–54, 82–108: X = 80 µm, Y = 68 µm
Chip thickness 400 µm
S1C17W14/W16 TECHNICAL MANUAL
(Rev. 1.2)
Die No. CJxxxxx
Y
(0, 0)
2.720 mm
Figure 1.3.2.2 S1C17W16 Pad Configuration Diagram (Chip)
X = 68 µm, Y = 80 µm
Seiko Epson Corporation
V
54
D2
V
53
DD
V
52
SS
#RESET
51
OSC1
50
OSC2
49
P14
48
P13
47
P12
46
P11
45
P10
44
P07
43
P06
42
X
P05
41
P04
40
P03
39
P02
38
P01
37
P00
36
PD2
35
PD1
34
PD0
33
V
32
PP
COM0
31
COM1
30
COM2
29
1 OVERVIEW
V
D2
V
DD
V
SS
#RESET
OSC1
OSC2
P14/UPMUX
P13/EXCL11/UPMUX
P12/EXCL10/UPMUX
P11/UPMUX/EXSVD
P10/EXOSC/UPMUX
P07/#BZOUT/UPMUX
P06/BZOUT/UPMUX
P05/EXCL01/UPMUX
P04/EXCL00/UPMUX
P03/RFIN0/UPMUX
P02/REF0/UPMUX
P01/SENA0/UPMUX
P00/SENB0/UPMUX
DCLK/PD2
DSIO/PD1
DST2/PD0
V
PP
COM0
COM1
COM2
1-9