Division - Epson S1C17W14 Technical Manual

Mode set-
Instruction
ting value
ld.ca %rd,%rs
0x04
or 0x05
(ext imm9)
ld.ca %rd,imm7
ld.ca %rd,%rs
0x14
or 0x15
(ext imm9)
ld.ca %rd,imm7
Example:
ld.cw %r0,0x04 ; Sets the mode (unsigned multiplication mode and 16 low-order bits output mode 0).
ld.ca %r0,%r1
ld.cw %r0,0x13 ; Sets the mode (operation result read mode and 16 high-order bits output mode 0).
ld.ca %r1,%r0

21.4 Division

The division function performs "A (32 bits) = B (32 bits) ÷ C (32 bits), D (32 bits) = remainder."
The following shows a procedure to perform a division:
1. Set the mode to 0x02 (initialize mode 2).
2 Set the 32-bit dividend (B) to the operation result register 0 using a "ld.cf" instruction.
3. Set the mode to 0x08 (unsigned division, 16 low-order bits output mode 0) or 0x09 (signed division, 16 low-
order bits output mode 0).
4. Send the 32-bit divisor (C) to COPRO2 using a "ld.ca" instruction.
5. Read the one-half result (16 low-order bits = A[15:0]) of the operation result register 0 (quotient) and the flag
status.
6. Set the mode to 0x13 (operation result read, 16 high-order bits output mode 0).
7. Read another one-half result (16 high-order bits = A[31:16]) of the operation result register 0 (quotient).
8. Set the mode to 0x23 (operation result read, 16 low-order bits output mode 1).
9. Read the one-half result (16 low-order bits = D[15:0]) of the operation result register 1 (remainder).
10. Set the mode to 0x33 (operation result read, 16 high-order bits output mode 1).
11. Read another one-half result (16 high-order bits = D[31:16]) of the operation result register 1 (remainder).
S1C17 Core
S1C17W14/W16 TECHNICAL MANUAL
(Rev. 1.2)
Table 21.3.1 Operation in Multiplication Mode
Operations
res0[31:0] ← %rd × %rs
%rd ← res0[15:0]
res0[31:0] ← %rd × imm7/16
%rd ← res0[15:0]
res0[31:0] ← %rd × %rs
%rd ← res0[31:16]
res0[31:0] ← %rd × imm7/16
%rd ← res0[31:16]
; Performs "res0[31:0] = %r0[15:0] × %r1[15:0]" and loads the 16 low-order bits of the
result to %r0.
; Loads the 16 high-order bits of the result to %r1.
COPRO2
Argument 2
Argument 1
Coprocessor
output
Flag output
Figure 21.4.1 Data Path in Initialize Mode 2
Seiko Epson Corporation
21 MULTIPLIER/DIVIDER (COPRO2)
Flags
psr (CVZN) ← 0b0000 The operation result register
16 bits
32 bits
Operation result
Operation result Operation result
register 1 register 0
Selector
Remarks
0 keeps the operation result
until it is rewritten by other
operation.
res0: operation result register 0
21-3