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0x43b0–0x43ba
Address
Register name
0x43b0 SPI0MOD
(SPIA Ch.0 Mode
Register)
0x43b2 SPI0CTL
(SPIA Ch.0 Control
Register)
0x43b4 SPI0TXD
(SPIA Ch.0 Transmit
Data Register)
0x43b6 SPI0RXD
(SPIA Ch.0 Receive
Data Register)
0x43b8 SPI0INTF
(SPIA Ch.0 Interrupt
Flag Register)
0x43ba SPI0INTE
(SPIA Ch.0 Interrupt
Enable Register)
0x43c0–0x43d2
Address
Register name
0x43c0 I2C0CLK
(I2C Ch.0 Clock
Control Register)
0x43c2 I2C0MOD
(I2C Ch.0 Mode
Register)
0x43c4 I2C0BR
(I2C Ch.0 Baud-Rate
Register)
0x43c8 I2C0OADR
(I2C Ch.0 Own
Address Register)
S1C17W14/W16 TECHNICAL MANUAL
(Rev. 1.2)
APPENDIX A LIST OF PERIPHERAL CIRCUIT CONTROL REGISTERS
Bit
Bit name
15–12 –
11–8 CHLN[3:0]
7–6 –
5
PUEN
4
NOCLKDIV
3
LSBFST
2
CPHA
1
CPOL
0
MST
15–8 –
7–2 –
1
SFTRST
0
MODEN
15–0 TXD[15:0]
15–0 RXD[15:0]
15–8 –
7
BSY
6–4 –
3
OEIF
2
TENDIF
1
RBFIF
0
TBEIF
15–8 –
7–4 –
3
OEIE
2
TENDIE
1
RBFIE
0
TBEIE
Bit
Bit name
15–9 –
8
DBRUN
7–6 –
5–4 CLKDIV[1:0]
3–2 –
1–0 CLKSRC[1:0]
15–8 –
7–3 –
2
OADR10
1
GCEN
0
–
15–8 –
7
–
6–0 BRT[6:0]
15–10 –
9–0 OADR[9:0]
Seiko Epson Corporation
Synchronous Serial Interface (SPIA) Ch.0
Initial
Reset
R/W
0x0
–
R
0x7
H0
R/W
0x0
–
R
0
H0
R/W
0
H0
R/W
0
H0
R/W
0
H0
R/W
0
H0
R/W
0
H0
R/W
0x00
–
R
0x00
–
R
0
H0
R/W
0
H0
R/W
0x0000
H0
R/W
0x0000
H0
R
0x00
–
R
0
H0
R
0x0
–
R
0
H0/S0
R/W
0
H0/S0
R/W
0
H0/S0
R
1
H0/S0
R
0x00
–
R
0x0
–
R
0
H0
R/W
0
H0
R/W
0
H0
R/W
0
H0
R/W
Initial
Reset
R/W
0x00
–
R
0
H0
R/W
0x0
–
R
0x0
H0
R/W
0x0
–
R
0x0
H0
R/W
0x00
–
R
0x00
–
R
0
H0
R/W
0
H0
R/W
0
–
R
0x00
–
R
0
–
R
0x7f
H0
R/W
0x00
–
R
0x000
H0
R/W
Remarks
–
–
–
–
–
Cleared by writing 1.
Cleared by reading the
SPI0RXD register.
Cleared by writing to the
SPI0TXD register.
–
I
2
C (I2C)
Remarks
–
–
–
–
AP-A-15
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