Interrupt; Control Registers; T16B Ch.n Clock Control Register - Epson S1C17W14 Technical Manual

15 16-BIT PWM TIMERS (T16B)

15.5 Interrupt

Each T16B channel has a function to generate the interrupt shown in Table 15.5.1.
Interrupt Interrupt flag
Capture T16BnINTF.CAPOWmIF
overwrite
Compare/ T16BnINTF.CMPCAPmIF When the counter value becomes equal to the compare buf-
capture
Counter MAX T16BnINTF.CNTMAXIF
Counter zero T16BnINTF.CNTZEROIF When the counter reaches 0x0000
T16B provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the interrupt
controller only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For
more information on interrupt control, refer to the "Interrupt Controller" chapter.

15.6 Control Registers

T16B Ch.n Clock Control Register

Register name Bit
T16BnCLK 15–9 –
8
7–4 CLKDIV[3:0]
3
2–0 CLKSRC[2:0]
Bits 15–9 Reserved
Bit 8 DBRUN
This bit sets whether the T16B Ch.n operating clock is supplied in DEBUG mode or not.
1 (R/W): Clock supplied in DEBUG mode
0 (R/W): No clock supplied in DEBUG mode
Bits 7–4 CLKDIV[3:0]
These bits select the division ratio of the T16B Ch.n operating clock (counter clock).
Bit 3 Reserved
Bits 2–0 CLKSRC[2:0]
These bits select the clock source of T16B Ch.n.
15-22
Table 15.5.1 T16B Interrupt Function
When the T16BnINTF.CMPCAPmIF bit =1 and the T16Bn
CCRm register is overwritten with new captured data in
capture mode
fer value in comparator mode
When the counter value is loaded to the T16BnCCRm regis-
ter by a capture trigger input in capture mode
When the counter reaches the MAX value
Bit name Initial
0x00
DBRUN 0
0x0
– 0
0x0
Seiko Epson Corporation
Set condition
Reset R/W
– R –
H0 R/W
H0 R/W
– R
H0 R/W
S1C17W14/W16 TECHNICAL MANUAL
Clear condition
Writing 1
Writing 1
Writing 1
Writing 1
Remarks
(Rev. 1.2)