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APPENDIX C MOUNTING PRECAUTIONS
(2) If a bypass capacitor is connected between V
tween the V
and V
DD
Signal line location
• To prevent electromagnetically-induced noise arising from mutual induction,
large-current signal lines should not be positioned close to pins susceptible to
noise, such as oscillator and analog measurement pins.
• Locating signal lines in parallel over significant distances or crossing signal
lines operating at high speed will cause malfunctions due to noise generated
by mutual interference.
• The SEG/COM lines and voltage boost/reduce capacitor drive lines are more
likely to generate noise, therefore keep a distance between the lines and pins
susceptible to noise.
Handling of light (for bare chip mounting)
The characteristics of semiconductor components can vary when exposed to light. ICs may malfunction or non-
volatile memory data may be corrupted if ICs are exposed to light.
Consider the following precautions for circuit boards and products in which this IC is mounted to prevent IC
malfunctions attributable to light exposure.
(1) Design and mount the product so that the IC is shielded from light during use.
(2) Shield the IC from light during inspection processes.
(3) Shield the IC on the upper, underside, and side faces of the IC chip.
(4) Mount the IC chip within one week of opening the package. If the IC chip must be stored before mounting,
take measures to ensure light shielding.
(5) Adequate evaluations are required to assess nonvolatile memory data retention characteristics before prod-
uct delivery if the product is subjected to heat stress exceeding regular reflow conditions during mounting
processes.
Unused pins
(1) I/O port (P) pins
Unused pins should be left open. The control registers should be fixed at the initial status.
(2) OSC1, OSC2, OSC3, OSC4, and EXOSC pins
If the OSC1 oscillator circuit, OSC3 oscillator circuit or EXOSC input circuit is not used, the OSC1 and
OSC2 pins, the OSC3 and OSC4 pins, or the EXOSC pin should be left open. The control registers should
be fixed at the initial status (disabled).
(3) V
, C
, SEGx, and COMx pins
C1–3
P1–2
If the LCD driver is not used, these pins should be left open. The control registers should be fixed at the
initial status (display off). The unused SEGx and COMx pins that are not required to connect should be left
open even if the LCD driver is used.
(4) C
and V
pins
V1–2
D2
If super economy mode is not used, the C
omitted by connecting between the V
C
is required even if super economy mode is not used.
PW3
Miscellaneous
Minor variations over time may result in electrical damage arising from disturbances in the form of voltages
exceeding the absolute maximum rating when mounting the product in addition to physical damage. The fol-
lowing factors can give rise to these variations:
(1) Electromagnetically-induced noise from industrial power supplies used in mounting reflow, reworking after
mounting, and individual characteristic evaluation (testing) processes
(2) Electromagnetically-induced noise from a solder iron when soldering
In particular, during soldering, take care to ensure that the soldering iron GND (tip potential) has the same po-
tential as the IC GND.
AP-C-2
DD
pins should be as short as possible.
SS
and C
V1
and V
DD
Seiko Epson Corporation
and V
, connections be-
SS
pins should be left open. In this case, C
V2
pins directly. When these pins are not short-circuited,
D2
S1C17W14/W16 TECHNICAL MANUAL
Bypass capacitor
connection example
V
V
DD
V
V
SS
C
C
PW1
PW1
Prohibited pattern
OSC1
OSC2
Large current signal line
High-speed signal line
can be
PW3
(Rev. 1.2)
DD
SS
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