Toshiba TMP91C815F Data Book page 21

3.3.3 System clock controller
The system clock controller generates the system clock signal (f
It contains two oscillation circuits and a clock gear circuit for high-frequency (fc) operation. The register
SYSCR1<SYSCK> changes the system clock to either fc or fs, SYSCR0<XEN> and SYSCR0<XTEN>
control enabling and disabling of each oscillator, and SYSCR1<GEAR0 to GEAR2> sets the
high-frequency clock gear to either 1, 2, 4, 8 or 16 (fc, fc/2, fc/4, fc/8 or fc/16). These functions can
reduce the power consumption of the equipment in which the device is installed.
The combination of settings <XEN> = 1, <XTEN> = 0, <SYSCK> = 0 and <GEAR0~GEAR2> = 100
will cause the system clock (f
For example, f
(1) Switching from Normal Mode to Slow Mode
When the resonator is connected to the X1 and X2 pins, or to the XT1 and XT2 pins, the warm-up
timer can be used to change the operation frequency after stable oscillation has been attained.
The warm-up time can be selected using SYSCR2<WUPTM0,WUPTM1>.
This warm-up timer can be programmed to start and stop as shown in the following examples 1
and 2.
Table 3.3.1 shows the warm-up time.
Note 1: When using an oscillator (other than a resonator) with stable oscillation, a warm-up timer is
not needed.
Note 2: The warm-up timer is operated by an oscillation clock. Hence, there may be some variation
in warm-up time.
Table 3.3.1 Warming-up times
Warming-up Time
SYSCR2
<WUPTM1,WUPTM0>
8
01 (2 / frequency)
14
10 (2 / frequency)
16
11 (2 / frequency)
) to be set to fc/32 (fc/16×1/2) after a Reset.
SYS
is set to 0.5 MHz when the 16-MHz oscillator is connected to the X1 and X2 pins.
SYS
Change to
Normal Mode
16 ( µ s)
1.024 (ms)
4.096 (ms)
91C815-18
) for the CPU core and internal I/O.
SYS
Change to
Slow Mode
at f
OSCH
fs
7.8 (ms)
500 (ms)
2000 (ms)
TMP91C815
= 16 MHz,
= 32.768 kHz