Toshiba TMP91C815F Data Book page 195

The watch dog timer consists of a 22-stage binary counter which uses the system clock (f
input clock. The binary counter can output f
outputs using WDMOD<WDTP1,WDTP0> generates a Watchdog interrupt and outputs watchdog timer
out when an overflow occurs as shown in Figure 3.12.2.
WDT Counter
n
WDT Interrupt
WDT Clear
(Soft ware )
The runaway detection result can also be connected to the Reset pin internally.
In this case, the reset time will be between 22 and 29 states as shown in Figure 3.12.3.
n
WDT Counter
WDT Interrupt
Internal Reset
/215, f
SYS SYS
Over flow
Figure 3.12.2 Normal mode
Over flow
22 to 29 states
(44 to 58 µ s @ f = 16 MHz, f
OSCH
Figure 3.12.3 Reset mode
91C815-192
/217, f /219 and /221. Selecting one of the
SYS fSYS
Write clear code
= 1 MHz)
FPH
TMP91C815
) as the
SYS
0