Page 1 Data Book 16bit Micro controller TLCS-900/L1 series TMP91C815F REV4.2 September 7, 2001 Rev. 4.2 05/September/2001...
Page 2: Table Of Contents
Table of Contents TLCS-900/L1 Devices TMP91C815F OUTLINE AND DEVICE CHARACTERISTICS 91C815-1 PIN ASSIGNMENT AND PIN FUNCTIONS 91C815-4 2.1 Pin Assignment Diagram 91C815-4 2.2 Pin Names and Functions 91C815-6 OPERATION 91C815-9 3.1 CPU 91C815-9 3.1.1 Reset 91C815-9 3.2 Memory Map 91C815-11 3.3 Triple clock, Stand-by function, Noise reduction...
Page 3 Data Book modification history REV/DATE REV/DATE REV/DATE REV/DATE page page page page Modification item Modification item Modification item Modification item Reason Reason Reason Reason Rev40/25-July-2001 13,16 Add to description of DFM operation 23,24 SBI: BIT2,3 Flocked ! Clocked SBI: modify the explanation of BIT6 SIO: SC0MOD0 ! SC1MOD0 CLK: bit0 Fc ! fs 225,6...
Page 4 TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications.
Page 5 TMP91C815 (8) LCD controller • Adapt to both Shift register type and Built-in RAM type LCD driver (9) Timer for real-time clock (RTC) • Based on TC8521A (10) Key-on wake up (Interrupt key input) (11) 10-bit A/D converter : 8 channels (12) Watch dog timer (13) Melody/Alarm generator •...
Page 6 KI0 to KI7 (P90 toP97) KEY-BOARD KO0 to KO 7(PA0 to PA7) PORT C PORT D MELODY/ MLDALM(PD7) D1BSCP (PD0) ALARM-OUT D2BLP (PD1) D3BFR (PD2) Controller ALARM,MLDALM(PD6) DLEBCD (PD3) DOFFB (PD4) Initial Function After Reset Figure 1.1 TMP91C815F Block Diagram 91C815-3...
Page 7: Tmp91C815F
TMP91C815 PIN ASSIGNMENT AND PIN FUNCTIONS The assignment of input/output pins for the TMP91C815F, their names and functions are as follows: Pin Assignment Diagram Figure 2.1 shows the pin assignment of the TMP91C815F. P55/BUSAK VREFL P54/BUSRQ AVSS P53/WAIT AVCC P52/HWR...
Page 8 TMP91C815 PAD Layout (Chip size 5.33mm ×5.35mm) Item (um) Name Name Name point point point point point point VREFL -2532 1982 -443 -2542 2524 AVSS -2532 1865 -323 -2542 2524 AVCC -2532 1748 -202 -2542 2524 1081 -2532 1435 -2542 2524 1209 -2532...
Page 9: Pin Names And Functions
TMP91C815 Pin Names and Functions The names of the input/output pins and their functions are described below. Table 2.2 Pin names and functions. Number Pin Name Functions of Pins D0 to D7 Data (lower): bits 0 to 7 of data bus P10 to P17 Port 1: I/O port that allows I/O to be selected at the bit level (When used to the external 8bit bus)
Page 10 TMP91C815 Pin Name Number Functions of Pins Port 70: I/O port Serial bus interface clock I/O data at SIO mode OPTRX0 Input Serial recive data “0” Port 71: I/O port Output Serial bus interface send data at SIO mode Serial bus interface send/recive data at I2C mode Open drain output mode by programmable (with pull up) OPTTX0 Output...
Page 11 TMP91C815 Pin Name Number Functions of Pins Port C2: I/O port SCLK0 Output Serial clock I/O 0 CTS0 Serial data send enable 0 (Clear to Send) Port C3: I/O port TXD1 Output Serial send data 1 Open drain output pin by programmable Port C4: I/O port RXD1 Input...
Page 12: Cpu
TMP91C815 OPERATION This following describes block by block the functions and operation of the TMP91C815F. Notes and restrictions for eatch book are outlined in “ 7, Precautions and Restrictions at the end of this manual. 3.1 CPU The TMP91C815 incorporates a high-performance 16-bit CPU (the 900/L1-CPU). For CPU operation, see the “TLCS-900/L1 CPU”.
Page 13 sampling sampling RESET A23∼0 0FFFF00H /CS0,1, 3, /CS2 DATA-IN DATA-IN D0∼15 (After reset released,,startting 2 wait read cycle) DATA-OUT D0∼15 (P52 input mode) XT1,XT2 Pull-up (internal) Note High-z...
Page 14: Memory Map
TMP91C815 3.2 Memory Map Figure 3.2.1 is a memory map of the TMP91C815. 000000H Internal I/O Direct (4KByte) area(n) 000100H 000FE0H 001000H 64Kbyte area Internal RAM (nn) (8K Byte) 003000H 010000H External memory 16Mbyte area (−R) (R+) (R + R8/16) (R + d8/16) (nnn) FFFF00H...
Page 15 TMP91C815 3.3 Triple Clock Function and Standby Function TMP91C815 contains (1) a clock gear, (2) clock doubler (DFM), (3) stand-by controller and (4) noise-reduction circuit. It is used for low-power, low-noise systems. This chapter is organized as follows. The clock operating modes are as follows: (a) Single Clock Mode (X1, X2 pins only), (b) Dual Clock Mode (X1, X2, XT1 and XT2 pins) and (c) Triple Clock Mode (the X1, X2, XT1 and XT2 pins and DFM).
Page 16 TMP91C815 Reset /32) OSCH release Reset instruction IDLE2 mode instruction interrupt (I/O operate) STOP mode NORMAL mode interrupt instruction (Stops all circuits) /gear value/2) OSCH IDLE1 mode interrupt (Operate only oscillator) Single clock mode transition figure Reset /32) OSCH instruction release Reset IDLE2 mode interrupt...
Page 17 TMP91C815 3.3.1 Block diagram of system clock SYSCR0<WUEF> SYSCR2<WUPTM1, WUPTM 0> DFMCR0<ACT1, ACT 0, DLUPTM> SYSCR0 Warming up timer (High/Low frequency φ T <PRCK1, PRCK 0> oscillator), Lock up timer (DFM) φ T0 fc/16 ÷ 2 ÷ 4 SYSCR0 <XTEN, RXTEN> Low-Frequency ÷...
Page 18 TMP91C815 3.3.2 SYSCR0 bit Symbol XTEN RXEN RXTEN RSYSCK WUEF PRCK1 PRCK0 (00E0H) Read/Write After reset High-frequen Low-frequen High-frequen Low-frequen Selects clock Warm-up Select prescaler clock cy oscillator cy oscillator cy oscillator cy oscillator after release Timer 00: f (fc) (fs) (fc) after (fs) after...
Page 19 TMP91C815 Symbol Name Address ACT1 ACT0 DLUPFG DLUPTM select f FPH Lock up Lock-up Time Control DFMCR0 0: 2 /f OSCH Status Flag f OSCH STOP STOP Register 0 1: 2 /f OSCH 0: end f OSCH 1: not end f DFM STOP f OSCH...
Page 20 TMP91C815 bit Symbol PROTECT TA3LCDE – – – EXTIN DRVOSCH DRVOSCL Read/Write EMCCR0 After reset (00E3H) Protect flag LCDC source Write “1” Write “0” Write “0” 1: External fc oscillator fs oscillator 0: OFF clock driver ability driver ability Function 1: ON 0: 32KHz 1: NORMAL...
Page 21 TMP91C815 3.3.3 System clock controller The system clock controller generates the system clock signal (f ) for the CPU core and internal I/O. It contains two oscillation circuits and a clock gear circuit for high-frequency (fc) operation. The register SYSCR1<SYSCK> changes the system clock to either fc or fs, SYSCR0<XEN> and SYSCR0<XTEN> control enabling and disabling of each oscillator, and SYSCR1<GEAR0 to GEAR2>...
Page 22 TMP91C815 Example 1-Setting the clock Changing from high frequency (fc) to low frequency (fs). SYSCR0 00E0H SYSCR1 00E1H SYSCR2 00E2H (SYSCR2), X − 11 − − X − B Sets warm-up time to 2 /fs. 6, (SYSCR0) Enables low-frequency oscillation. 2, (SYSCR0) Clears and starts warm-up timer.
Page 23 TMP91C815 Example 2-Setting the clock Changing from low frequency (fs) to high frequency (fc). SYSCR0 00E0H SYSCR1 00E1H SYSCR2 00E2H (SYSCR2), X − 10 − − X − B Sets warm-up time to 2 /fc. 7, (SYSCR0) Enables high-frequency oscillation. 2, (SYSCR0) Clears and starts warm-up timer.
Page 24 TMP91C815 (2) Clock gear controller When the high-frequency clock fc is selected by setting SYSCR1<SYSCK> = 0, f is set according to the contents of the Clock Gear Select Register SYSCR1<GEAR0 to GEAR2> to either fc, fc/2, fc/4, fc/8 or fc/16. Using the clock gear to select a lower value of f reduces power consumption.
Page 25 TMP91C815 3.3.4 Prescaler clock controller For the internal I/O (TMRA01 to 23, SIO0 to 1) there is a prescaler which can divide the clock. The φT0 clock input to the prescaler is either the clock f divided by 4 or the clock fc/16 divided by 4.
Page 26 TMP91C815 Limitation point on the use of DFM It’s prohibited to execute DFM enable/disable control in the SLOW mode(fs) (write to DFMCR0<ACT1:0>=”10”). You should control DFM in the NORMAL mode. 2. If you stop DFM operation during using DFM (DFMCR0<ACT1:0>=”10”) , you shouldn’t execute the commands that change the clock f to f and stop the DFM at the same time.
Page 27 TMP91C815 （２） Change / Stop Control (OK) DFM use mode (f )→ DFM Stop )→ High frequency oscillator operation mode(f OSCH → Low frequency oscillator operation mode(f )→High frequency oscillator stop (DFMCR0),11------B ; Change the system clock f to f OSCH (DFMCR0),00------B ;...
Page 28 TMP91C815 3.3.6 Noise reduction circuits Noise reduction circuits are built in, allowing implementation of the following features. (1) Reduced drivability for high-frequency oscillator (2) Reduced drivability for low-frequency oscillator (3) Single drive for high-frequency oscillator (4) SFR protection of register contents (5) ROM protection of register contents (6) Release from hard protection The above functions are performed by making the appropriate settings in the EMCCR0...
Page 29 TMP91C815 (2) Reduced drivability for low-frequency oscillator (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) X1 pin Enable oscillation Resonato EMCCR0<DRVOSCL> XT2 pin (Setting method) The drivability of the oscillator is reduced by writing 0 to the EMCCR0<DRVOSCL> register. By Reset, <DRVOSCL>...
Page 30 TMP91C815 (4) Runaway provision with SFR protection register (Purpose) Provision in runaway of program by noise mixing. Write operation to specified SFR is prohibited so that provision program in runaway prevents that it is it in the state which is fetch impossibility by stopping of clock, memory control register (CS/WAIT controller, MMU) is changed.
Page 31 TMP91C815 (5) Runaway provision with ROM protection register (Purpose) Provision in runaway of program by noise mixing. (Operation explanation) When write operation was executed for external three kinds of ROM by runaway of program, INTP1 is occurred and detects runaway function. Three kinds of ROM is fixed as for Flash-ROM(Option-Program ROM), Data-ROM, Program-ROM are as follows on the logical address memory map.
Page 32 TMP91C815 3.3.7 Standby controller (1) Halt Modes When the HALT instruction is executed, the operating mode switches to Idle2, Idle1 or Stop Mode, depending on the contents of the SYSCR2<HALTM1,HALTM0> register. The subsequent actions performed in each mode are as follows: ! IDLE2: Only the CPU halts.
Page 33 TMP91C815 (2) How to release the Halt mode These HALT states can be released by resetting or requesting an interrupt. The halt release sources are determined by the combination between the states of interrupt mask register <IFF2-0> and the halt modes. The details for releasing the HALT status are shown in Table 3.3 4. •...
Page 34 TMP91C815 Table 3.3.4 Source of Halt state clearance and Halt clearance operation Interrupt Enabled Interrupt Disabled Status of Received Interrupt (interrupt level) ≥ (interrupt mask) (interrupt level) < (interrupt mask) Halt mode Idle2 Idle1 Stop Idle2 Idle1 Stop − − −...
Page 35 TMP91C815 (3) Operation A. IDLE2 Mode In Idle2 Mode only specific internal I/O operations, as designated by the Idle2 Setting Register, can take place. Instruction execution by the CPU stops. Figure 3.3 6 illustrates an example of the timing for clearance of the Idle2 Mode Halt state by an interrupt.
Page 36 TMP91C815 STOP Mode When Stop Mode is selected, all internal circuits stop, including the internal oscillator Pin status in Stop Mode depends on the settings in the SYSCR2<DRVE> register. Table 3.3.6 summarizes the state of these pins in Stop Mode. After Stop Mode has been cleared system clock output starts when the warm-up time has elapsed, in order to allow oscillation to stabilize.
Page 37 TMP91C815 (Setting Example) The Stop mode is entered when the low frequency operates, and high frequency operates after releasing due to NMI. Address SYSCR0 00E0H SYSCR1 00E1H SYSCR2 00E2H 8FFDH (SYSCR1), 08H = fs/2 (SYSCR2), X − 1001X1B 9000H ; Sets Warming Up Time to 2 OSCH (SYSCR0), 011000 −...
Page 38 TMP91C815 Table 3.3.6 Pin states in IDLE1/Stop Mode <DRVE> = 0 <DRVE> = 1 Pin name Input/Output D0 ∼ 7 − − P10 ∼ 17(D8 ∼ 15 − − Input mode − Output mode Output − − P20 ∼ 27(A16 ∼ 23),A0 ∼ 15,P Output pin Output −...
Page 39: Interrupts
TMP91C815 3.4 Interrupts Interrupts are controlled by the CPU Interrupt Mask Register SR<IFF2:0> and by the built-in interrupt controller. The TMP91C815 has a total of 39 interrupts divided into the following five types: • Interrupts generated by CPU: 9 sources (Software interrupts,Illegal Instruction interrupt) •...
Page 40 TMP91C815 Interrupt processing Micro DMA soft start request Interrupt specified Presupposes that one of four by micro DMA channels of micro DMA start start vector? vector register is set to FCH. Clear interrupt requenst flag Data transfer by micro Interrupt vector value “V” read Interrupt request F/F clear General-purpose...
Page 41 TMP91C815 3.4.1 General-purpose interrupt processing When the CPU accepts an interrupt, it usually performs the following sequence of operations. That is also the same as TLCS-900/L and TLCS-900/H. (1) The CPU reads the interrupt vector from the interrupt controller. If the same level interrupts occur simultaneously, the interrupt controller generates an interrupt vector in accordance with the default priority and clears the interrupt request.
Page 42 TMP91C815 Table 3.4.1 TMP91C815 interrupt vectors table Default Vector Micro Vector reference Type Interrupt source and source of micro DMA request Priority value(V) Address start vector "Reset" or ｢SWI 0」instruction − 0000H FFFF00H 「SWI 1」instruction − 0004H FFFF04H INTUNDEF: illegal instruction or ｢SWI 2」instruction −...
Page 43 TMP91C815 3.4.2 Micro DMA processing In addition to general-purpose interrupt processing, the TMP91C815 supprots a micro DMA function. Interrupt requests set by micro DMA perform micro DMA processing at the highest priority level (level 6) among maskable interrupts, regardless of the priority level of the particular interrupt source. Micro. The micro DMA has 4 channels and is possible continuous transmission by specifing the say later burst mode.
Page 44 TMP91C815 Three micro DMA transfer modes are supported: 1-byte transfer, 2-byte (one-word) transfer, and 4-byte transfer. After a transfer in any mode, the transfer source / destination addresses are increased, decreased, or remain unchanged. This simplifies the transfer of data from I/O to memory, from memory to I/O , and from I/O to I/O. For details of the transfer modes, see 3.4.2 (4) “Transfer Mode Register”.
Page 45 TMP91C815 (2) Soft start function In addition to starting the micro DMA function by interrupts, TMP91C815 includes a micro DMA software start function that starts micro DMA on the generation of the write cycle to the DMAR register. Writing “1” to each bit of DMAR register causes micro DMA once. At the end of transfer, the corresponding bit of the DMAR register is automatically cleared to “0”.
Page 46 TMP91C815 (4) Detailed description of the Transfer Mode Register 8 bits DMAM0 to (note): When setting a value in this register, write 0 to the upper 3 Mode DMAM3 bits. Number of Minimum Number of Mode Description Execution States Execution Time Transfer Bytes @ fc = 16 MHz Transfer Destination Address INC Mode...
Page 47 TMP91C815 3.4.3 Interrupt controller operation The block diagram in Figure 3.4.3 shows the interrupt circuits. The left-hand side of the diagram shows the interrupt controller circuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circuit. For each of the 36 interrupt channels there is an interrupt request flag (consisting of a flip-flop), an interrupt priority setting register and a micro DMA start vector register.
Page 48 Interrupt controller Interrupt request F/F RESET interrupt Interrupt RESET vector read V = 20H mask F/F INTWD V = 24H Interrupt request Decoder Priority setting register ∼ Priority encoder IFF2:0 EI 1 signal to CPU Dn + 1 Interrupt Highest INTRQ2 ∼...
Page 49 TMP91C815 (1) Interrupt level setting registers Symbol NAME Address INTAD INT0 INT0 & IADC IADM2 IADM1 IADM0 I0M2 I0M1 I0M0 INTAD INTE0AD Enable INT2 INT1 INT1 & I2M2 I2M1 I2M0 I1M2 I1M1 I1M0 INT2 INTE12 Enable INTALM4 INT3 INT3& IA4C IA4M2 IA4M1 IA4M0...
Page 50 TMP91C815 Symbol NAME Address INTTX0 INTRX0 Interrupt ITX0C ITX0M2 ITX0M1 ITX0M0 IRX0C IRX0M2 IRX0M1 IRX0M0 Enable INTES0 Serial 0 INTTX1 INTRX1 INTRX1 & ITXT1C ITX1M2 ITX1M1 ITX1M0 IRX1C IRX1M2 IRX1M1 IRX1M0 INTTX1 INTES1 Enable INTLCD INTS2 INTES2 & INTES2 ILCD1C ILCDM2 ILCDM1 ILCDM0...
Page 51 TMP91C815 (2) External interrupt control Symbol NAME Address I3EDGE I2EDGE I1EDGE I0EDGE I0LE NMIREE Interrupt Input Always INT3EDGE INT2EDGE INT1EDGE INT0EDGE INT0 mode 1: Operates IIMC Mode 0: Rising 0: Rising 0: Rising 0: Rising 0: Edge write”0” even on (no RMW) control 1: Falling...
Page 52 TMP91C815 Symbol NAME Address DMA0 Start Vector DMA0 DMA0V5 DMA0V4 DMA0V3 DMA0V2 DMA0V1 DMA0V0 DMA0V Start Vector DMA1 Start Vector DMA1 DMA1V5 DMA1V4 DMA1V3 DMA0V2 DMA1V1 DMA1V0 DMA1V Start Vector DMA2 Start Vector DMA2 DMA2V5 DMA2V4 DMA2V3 DMA2V2 DMA2V1 DMA2V0 DMA2V Start Vector...
Page 53 TMP91C815 (6) Attention point The instruction execution unit and the bus interface unit of this CPU operate independently. Therefore, immediately before an interrupt is generated, if the CPU fetches an instruction that clears the corresponding interrupt request flag, the CPU may execute the instruction that clears the interrupt request flag(*1) between accepting and reading the interrupt vector.
Page 54 TMP91C815 3.5 Port Functions The TMP91C815 features 61 bit settings which relate to the various I/O ports. As well as general-purpose I/O port functionality, the port pins also have I/O functions which relate to the built-in CPU and internal I/Os. Table 3.5.1 lists the functions of each port pin. Table 3.5.2 lists I/O registers and their specifications.
Page 55 TMP91C815 I/O register Port Pin name Specification PnCR PnFC PnFC2 Port 1 P10 to P 17 Input port None None (note1) Output port D8 to D15 bus Port 2 P20 t o P 27 Output port None A16 to A23 output Port 5 P52 to P56 Input port (Without PU)
Page 56 TMP91C815 Table 3.5.2 I/O Registers and Specifications (2/2) X: Don’t care I/O register Port Pin name Specification PnCR PnFC PnFC2 Port 8 P80 to P87 Input port AN0 to 7 input (note5) None ADTRG input (note6) Port 9 P90 to P97 Input port None KI0 to 7 input...
Page 57 TMP91C815 After Reset, the port pins listed below function as general-purpose I/O port pins. Resetting sets I/O pins, which can be programmed for either input or output to be input ports pins. Setting the port pins for internal function use must be done in software. Note about bus release and programmable pull-up I/O port pins When the bus is released (i.e.
Page 58: Port
TMP91C815 3.5.1 Port 1 (P10 to P17) Port 1 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P1CR. Resetting , the control register P1CR to “0” and sets Port 1 to input mode. In addition to functioning as a general-purpose I/O port, Port 1 can also function as data bus (D8 to 15).
Page 59: Port
TMP91C815 3.5.2 Port 2 (P20 to P27) Port 2 is an 8-bit output port. In addition to functioning as a output port, Port 2 can also function as an address bus (A16 to A23). Each bit can be set individually for address bus using the function register P2FC. Resetting sets all bits of the function register P2FC to 1 and sets Port 2 to address bus.
Page 60 TMP91C815 Port 1 Register bit Symbol (0000H) (0001H) Read/Write After Reset Input mode (Output latch register is cleared to 0.) Port 1 Control Register P1CR bit Symbol P17C P16C P15C P14C P13C P12C P11C P10C (0004H) Read/Write After Reset Function 0: IN 1: OUT Port 1 I/O setting 0: Input...
Page 61 TMP91C815 3.5.3 Port 5 (P52 to P56) Port 5 is an 5-bit general-purpose I/O port. I/O is set using control register P5CR and P5FC. Resetting resets all bits of the output latch P5 to “1”, the control register P5CR and the function register P5FC to “0” and sets P52 to P56 to input mode with pull-up register.
Page 62 TMP91C815 Reset Direction control (on bit basis) (Programmable P-ch P5CR Write Pull-up) P53 (WAIT) Output Latch Output buffer P5 Write P5 Read Internal WAIT Reset Direction control (on bit basis) P5CR Write Function contorol (on bit basis) (Programmable P5FC Write P-ch Pull-up) ...
Page 63 TMP91C815 Port 5 Register bit Symbol (000DH) Read/Write After reset Input mode (With Pull-up) Port 5 Control Register P5CR bit Symbol P56C P55C P54C P53C P52C (000AH) Read/Write After reset 0: IN 1: OUT II/O setting 0 Input 1 Output Port 5 function register −...
Page 64: Port
TMP91C815 3.5.4 Port6 (P60 to P67) Port60 to 67 are 8bit output ports. Resetting sets output latch of P62 to “0” and output latchs of P60 to P61,P63 to P67 to “1”. Port6 also function as chip-select output(/CS0 to /CS3), extend address output(EA24,EA25) and extend chip-select output(/CS2A,/CS2B,/CS2C,/CS2D,/CS2E).
Page 65 TMP91C815 3.5.5 Port7 (P70 to P77) Port 7 is an 8-bit general-purpose I/O port. I/O can be set on bit basis using the control register. Resetting sets Port 7 to input port and all bits of output latch to”1”. In addition to functioning as a general-purpose I/O port, Port 7 also functions as follows. 1.
Page 66 TMP91C815 (2) Port71 (SO/SDA/OPTTX0) Port71 is a general-purpose I/O port. It is also used as SDA (data input for I C mode), SO (data output for SIO mode) for serial bus interface and OPTTX0 (transmit output for IrDA mode of SIO0).
Page 67 TMP91C815 (3) Port 72 (SI/SCL) Port72 is a general-purpose I/O port. It is also used as SI (data input for SIO mode), SCL (clock input/output for I C mode) for serial bus interface and input for release hard-protect. Reset Direction control (on bit basis) P7CR write...
Page 68 TMP91C815 (4) Port 73 (/CS2F),74(/CS2G),75(/CSEXA) Port73 to 75 are general-purpose I/O ports. These are also used as control signal for extend chip-select output. Reset Function control 2 (on bit basis) P7FC2 write Direction control (on bit basis) P7CR write Funtcion control (on bit basis) P73(/CS2F),...
Page 69 TMP91C815 (5) Port 76(MSK),77(VEECLK) Port76 and 77 are general-purpose I/O ports. These are also used as clock control function for voltage booster of external LCD driver. MSK pin (P76) is a input pin from external LCD driver, clock output from VEECLK pin is controlled by state of this pin.
Page 70 TMP91C815 Port 7 Register bit Symbol (0013H) Read/Write Input mode After reset Port 7 Control Register P7CR bit Symbol P77C P76C P75C P74C P73C P72C P71C P70C (0016H) Read/Write After reset 0: IN 1: OUT Port 7 Function Register bit Symbol P77F P76F...
Page 71: Port 8
TMP91C815 3.5.6 Port 8 (P80 to P87) Port 8 is an 8-bit input port and can also be used as the analog input pins for the internal A/D converter. P83 can also be used as ADTRG pin for the A/D converter. Port 8 P80 to P87 Port 8 read...
Page 72 TMP91C815 3.5.7 Port 9 (P90 to P97) Port 90 to 97 are 8-bit input ports with pull-up resistors. In addition to functioning as general-purpose I/O port, port 90 to 97 can also Key-on wake-up function as Key board interface. The various functions can each be enabled by writing “1”...
Page 73 TMP91C815 3.5.8 Port A (PA0 to PA7) Port A0 to A7 are 8-bit output ports, and also used Key board interface pin KO0 to KO7 which can set open drain output buffer. Writing “1” to the corresponding bit of the port A function register (PAFC) enable the open drain output.
Page 74 TMP91C815 3.5.9 Port B (PB0 to PB6) Port B0 to PB6 is a 7-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets Port B to be an input port. In addition to functioning as a general-purpose I/O port, Port B0 has clock input terminal TA0IN of 8 bits timer 0, and port B1, B2 each has facility of 8 bits timer listing TA1OUT, TA3OUT terminal.
Page 75 TMP91C815 (2) PB3 (INT0), PB4 (INT1)-PB6 (INT3) Reset Direction Control (on bits basis) PBCR write Function control (on bits basis) PBFC write Output latch PB3 (INT0) PB write Selector PB read Level / edge select & INT0 Raising/Falling select IIMC<I0LE, I0EDGE> Figure 3.5.24(2) Port B3 Reset Direction Control...
Page 76 TMP91C815 Port B Register bit Symbol (0022H) Read/Write After Reset Input Mode Port B Control Register PBCR bit Symbol PB6C PB5C PB4C PB3C PB2C PB1C PB0C (0024H) Read/Write After Reset 0: IN 1: OUT Port B Function Register bit Symbol PB6F PB5F PB4F...
Page 77 TMP91C815 3.5.10 Port C (PC0 to PC5) Port C0 to C5 are 6-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets PC0 to PC5 to be an input ports. It also sets all bits of the output latch register to “1”.
Page 78 TMP91C815 (2) Port C1, C4 (RXD0, 1) Port C1 and C4 are I/O port pins and can also is used as RXD input for the serial channels. In case of use RXD0/RXD1, it is possible to logical invert by setting the register PC<PC1,PC4>. And input data of SIO0 can be select from RXD/PC1 pin or OPTRX0/P70 by setting the register PCFC2<P70F2>.
Page 79 TMP91C815 Port C Register bit Symbol (0023H) Read/Write After Reset Input mode Port C Control Register PCCR bit Symbol PC5C PC4C PC3C PC2C PC1C PC0C (0026H) Read/Write After Reset 0: IN 1: OUT Port C Functon Register bit Symbol PC5F PC3F PC2F...
Page 80 TMP91C815 3.5.11 Port D (PD0 to PD7) Port D is an 8-bit output port. Resetting sets the output latch PD to “1”, and PD0 to PD7 pin output “1”. In addition to functioning as output port, Port D also function as output pin for LCD controller (D1BSCP,D2BLP,D3BFR,DLEBCD and DOFFB), output pin for internal clock (SCOUT), output pin for RTC alarm (/ALARM) and output pin for melody/alarm generator (MLDALM,/MLDALM).
Page 81 TMP91C815 Reset Function control (On bit basis) PDFC write Output latch PD6 (/ALARM, Selector /MLDALM) PD write PD read /MLDALM Selector /ALARM Figure 0.28(3) Port D Port D register bit Symbol (0029H) Read/Write After Reset Port D function register PDFC bit Symbol PD7F PD6F...
Page 82: Chip Select/Wait Controller
TMP91C815 3.6 Chip Select/Wait Controller On the TM91C815, four user-specifiable address areas (CS0 to CS3) can be set. The data bus width and the number of waits can be set independently for each address area (CS0 to CS3 and others). The pins /CS0 to /CS3 (which can also function as port pins P60 to P63) are the respective output pins for the areas CS0 to CS3.
Page 83 TMP91C815 (1) Memory Start Address Registers Figure 3.6.1 shows the Memory Start Address Registers. The Memory Start Address Registers MSAR0 to MSAR3 set the start addresses for the CS0 to CS3 areas. Set the upper eight bits (A23 to A16) of the start address in <S23: S16>. The lower 16 bits of the start address (A15 to A0) are permanently set to 0.
Page 84 TMP91C815 (2) Memory Address Mask Registers Figure 3.6.3 shows the Memory Address Mask Registers. Memory address mask registers MAMR0 to MAMR3 are used to set the size of the CS0 to CS3 areas by specifying a mask for each bit of the start address set in memory start address registers MAMR0 to MAMR3. The compare operation used to determine if an address is in the CS0 to CS3 areas is only performed for bus address bits corresponding to bits set to “0”...
Page 85 TMP91C815 (3) Setting Memory Start Addresses and Address Areas Figure 3.6.4 show an example of specifying a 64K-byte address area starting from 010000H using the CS0 areas. Set “01H” in memory start address register MSAR0<S23 to S16>(corresponding to the upper 8 bits of the start address).
Page 86 TMP91C815 (4) Address Area Size Specification Table 3.6.1 shows the relationship between CS area and area size.△ Indicates areas that cannot be set by memory start address register and address mask register combinations. When setting an area size using a combination indicated by △ , set the start address mask register in the desired steps starting from 000000H.
Page 87 TMP91C815 Chip Select/Wait Control Register B0CS Bit symbol B0OM1 B0OM0 B0BUS B0W2 B0W1 B0W0 (00C0H) Read/Write After Reset Read- 0: Disable Chip Select output Data bus Number of Waits Modify- 1: Enable waveform selection width 000: 2 waits 100: reserved Write 00: For ROM/SRAM 0: 16 bits...
Page 88 TMP91C815 (1) Master Enable bits Bit 7 (<B0E>, <B1E>, <B2E> or <B3E>) of a chip select/wait control register is the master bit which is used to enable or disable settings for the corresponding address area. Writing “1” to this bit enables the settings.
Page 89 TMP91C815 (3) Wait control Bits 0 to 2 (<B0W0 to B0W2>, <B1W0 to B1W2>, <B2W0 to B2W2>, <B3W0 to B3W2>, <BEXW0 to BEXW2>) of a chip select/wait control register specify the number of waits that are to be inserted when the corresponding memory area is accessed. The following types of wait operation can be specified using these bits.
Page 90 TMP91C815 (6) Procedure for setting chip select/wait control When using the chip select/wait control function, set the registers in the following order: Set the Memory Start Address Registers MSAR0 to MSAR3. Set the start addresses for CS0 to CS3. " Set the Memory Address Mask Registers MAMR0 to MAMR3.
Page 91 TMP91C815 3.6.3 Connecting external memory Figure 3.6.6 shows an example of how to connect external memory to the TMP91C815. In this example the ROM is connected using a 16-bit bus. The RAM and I/O are connected using an 8-bit bus. TMP91C815 /CS0 /CS1...
Page 92: 8-Bit Timers(Tmra) 91C815-89
TMP91C815 3.7 8-bit Timers (TMRA) The TMP91C815 features 4 channel(TMRA0 to TMRA3) built-in 8-bit timers. These timers are paired into 2 modules: TMRA01 and TMRA23. Each module consists of 2 channels and can operate in any of the following 4 operating modes. •...
Page 93 Prescaler Prescaler Run/Clear TA01RUN clock: φT0 <TA01PRUN> φT1 φT4 φT16 φT256 Timer Timer flip-flop Flip-Flop output: TA1FF TA01RUN<TA0RUN> TA1OUT TA01RUN<TA1RUN> Selector Selector External input TA1FFCR clock: TA0IN φT1 φT1 8-Bit Up-Counter 8-bit up counter φT4 φT16 (UC1) (UC0) φT256 φT16 −1 Over flow TA01MOD...
Page 94 Prescaler Prescaler Run/clea TA23RUN clock: φT0 <TA23PRUN> φT1 φT4 φT16 φT256 Timer Timer flip-flop flip-flop output: TA3FF TA3OUT TA23RUN<TA2RUN> TA23RUN<TA3RUN> Selector Selector TA3FFCR φT1 φT1 8-bit Up-Counter 8-bit Comparator φT4 φT16 (UC2) (UC3) φT16 φT256 −1 Over flow TA23MOD TA23MOD TA23MOD <TA2CLK1, TA2CLK 0>...
Page 95 TMP91C815 3.7.2 Operation of each circuit (1) Prescalers A 9-bit prescaler generates the input clock to TMRA01. The “PHI_T0” as the input clock to prescaler is a clock divided by 4 which selected using the Prescaler Clock Selection Register SYSCR0<PRCK1,PRCK0>. The prescaler’s operation can be controlled using TA01RUN<TA0PRUN>...
Page 96 TMP91C815 (3) Timer registers (TA0REG and TA1REG) These are 8-bit registers which can be used to set a time interval. When the value set in the timer register TA0REG or TA1REG matches the value in the corresponding up-counter, the Comparator Match Detect signal goes Active.
Page 97 TMP91C815 (4) Comparator (CP0) The comparator compares the value in an up counter with the value set in a timer register. If they match, the up counter is cleared to zero and an interrupt signal (INTTA0 or INTTA1) is generated. If timer flip-flop inversion is enabled, the timer flip-flop is inverted at the same time.
Page 98 TMP91C815 3.7.3 SFRs TMRA01 Run Register TA01RUN Bit symbol TA0RDE I2TA01 TA1RUN TA0RUN TA01PRUN (0100H) Read/Write After Reset Double IDLE2 Timer Run/Stop control buffer 0: Stop 0: Stop & Clear Function 0: Disable 1: Operate 1: Run (count up) 1: Enable TA0REG double buffer control Timer Run/Stop control Disable...
Page 99 TMP91C815 TMRA01 Mode Register TA01MOD Bit symbol TA01M1 TA01M0 PWM01 PWM00 TA1CLK1 TA1CLK0 TA0CLK1 TA0CLK0 (0104H) Read/Write After Reset Operation mode PWM cycle Source clock for TMRA1 Source clock for TMRA0 00: 8-Bit Timer Mode 00: reserved 00: TA0TRG 00: TA0IN pin 01: φ...
Page 100 TMP91C815 TMRA23 Mode Register TA23MOD Bit Symbol TA23M1 TA23M0 PWM21 PWM20 TA3CLK1 TA3CLK0 TA2CLK1 TA2CLK0 (010CH) Read/Write After Reset Operation mode PWM cycle TMRA3 clock for TMRA3 TMRA2 clock for TMRA2 00: 8-Bit Timer Mode 00: reserved 00: TA2TRG 00: reserved 01: φ...
Page 101 TMP91C815 TMRA1 Flip-Flop Control Register TA1FFCR Bit symbol TAFF1C1 TAFF1C0 TAFF1IE TAFF1IS (0105H) Read/Write After Reset TA1FF 00: Invert TA1FF TA1FF 01: Set TA1FF Control for Inversion Read- 10: Clear TA1FF inversion select Modify-Write Function instructions 11: Don’t care 0: Disable 0: TMRA0 1: Enable 1: TMRA1...
Page 102 TMP91C815 TMRA3 Flip-Flop Control Register TA3FFCR Bit symbol TAFF3C1 TAFF3C0 TAFF3IE TAFF3IS (010DH) Read/Write After Reset 00: Invert TA3FF TA3FF TA3FF 01: Set TA3FF Control for Inversion Read- 10: Clear TA3FF inversion select Modify-Write Function 11: Don’t care 0: Disable 0: TMRA2 instructions 1: Enable...
Page 103 TMP91C815 3.7.4 Operation in each mode (1) 8-Bit Timer Mode Both TMRA0 and TMRA1 can be used independently as 8-bit interval timers. Setting its function or counter data for TMRA0 and TMRA1 after stop these registers. Generating interrupts at a fixed interval (using TMRA1) To generate interrupts at constant intervals using TMRA1 (INTTA1), first stop TMRA1 then set the operation mode, input clock and a cycle to TA01MOD and TA1REG register, respectively.
Page 104 TMP91C815 " Generating a 50% duty ratio square wave pulse The state of the timer flip-flop (TA1FF) is inverted at constant intervals and its status output via the timer output pin (TA1OUT). Example: To output a 3.0-µs square wave pulse from the TA1OUT pin at fc = 16 MHz, use the following procedure to make the appropriate register settings.
Page 105 TMP91C815 Making TMRA1 count up on the match signal from the TMRA0 comparator Select 8-Bit Timer Mode and set the comparator output from TMRA0 to be the input clock to TMRA1. Comparaot output (TMRA0 match) TMRA0 up-counter (when TA0REG = 5) TMRA1 up-counter (when TA1REG = 2) TMRA1 match output...
Page 106 TMP91C815 The comparator match signal is output from TMRA0 each time the up-counter UC0 matches TA0REG, though the up-counter UC0 is not be cleared and also INTTA0 is not generated. In the case of the TMRA1 comparator, the match detect signal is output on each comparator pulse on which the values in the up-counter UC1 and TA1REG match.
Page 107 TMP91C815 In this mode, a programmable square wave is generated by inverting the timer output each time the 8-bit up-counter (UC0) matches the value in one of the timer registers TA0REG or TA1REG. The value set in TA0REG must be smaller than the value set in TA1REG. Although the up-counter for TMRA1 (UC1) is not used in this mode, TA01RUN<TA1RUN>...
Page 108 TMP91C815 Example: To generate 1/4-duty 50-kHz pulses (at fc = 16 MHz): 20 µ s ∗ Clock state System clock: High frequency (fc) Clock gear: 1 (fc) Prescaler clock: f Calculate the value which should be set in the timer register. To obtain a frequency of 50 kHz, the pulse cycle t should be: t = 1/50 kHz = 20 μsec φT1 = 0.5 µsec (at 16 MHz);...
Page 109 TMP91C815 (4) 8-Bit PWM Output Mode This mode is only valid for TMRA0. In this mode, a PWM pulse with the maximum resolution of 8 bits can be output. When TMRA0 is used the PWM pulse is output on the TA1OUT pin (which is also used as P71). TMRA1 can also be used as an 8-bit timer.
Page 110 TMP91C815 − 1 overflow is In this mode, the value of the register buffer will be shifted into TA0REG if 2 detected when the TA0REG double buffer is enabled. Use of the double buffer facilitates the handling of low duty ratio waves. Match with TA0REG Up-counter = Q Up-counter = Q...
Page 111 TMP91C815 Table 3.7.3 PWM cycle @fc = 16 MHz, fs = 32.768 kHz Select System Select Prescaler PWM cycle Gear Value − 1 − 1 − 1 Clock Clock <GEAR2 ∼ GEAR0> <PRCK1 ∼ PRCK0> φ T1 φ T4 φ T16 φ...
Page 112 TMP91C815 3.8 External memory extension function (MMU) This is MMU function which can expand program / data area to 136M byte by having 4 local area. Address pins to external memory are 2 extended address bus pins (EA24,EA25) and 8 extended chip select pins (/CS2A to /CS2G and /CSEXA) in addition to 24 address bus pins (A0 〜...
Page 113 TMP91C815 3.8.1 Recommendable memory map The recommendation logic address memory map at the time of varieties extension memory correspondence is shown in Figure 3.8.1.1. And, a physical-address map is shown in Figure 3.8.1.2. However, when memory area is less than 16M bytes and is not expanded, please refer to section of CS/WAIT controller.
Page 114 TMP91C815 LOCAL0 LOCAL1 LOCAL2 LOCAL3 91C815 /CS1 /CS3 /CS2A for Data-ROM for Option for Data-RAM for Program-ROM (16MB × 6) Program-ROM (8MB) (16MB) /CS2B /CS2E (16MB) 000000H BANK0 BANK0 BANK0 BANK1 BANK2 BANK12 BANK1 BANK1 BANK0 BANK3 BANK4 Internal-I/O & RAM BANK2 BANK2 BANK5...
Page 115 TMP91C815 3.8.2 Block diagram A2 to A16 CPU out LOCAL3 Area Decoder Address detect signal A23 to A8 A23 to A20 Physical address LOCAL0 register EA22 to EA20 VA26 to VA20 Physical Selector LOCAL1 register EA23 to EA21 Address WA26 to WA7 LOCAL2 register EA23 to EA21 (To external...
Page 116 TMP91C815 LOCAL0 register LOCAL0 bit Symbol L0EA22 L0EA21 L0EA20 (0350H) Read/Write After reset Use BANK Setting BANK number for LOCAL0 Function LOCAL0 0: not use 1: use LOCAL1 register LOCAL1 bit Symbol L1EA23 L1EA22 L1EA21 (0351H) Read/Write After reset Use BANK Setting BANK number for LOCAL1 Function LOCAL1...
Page 117 TMP91C815 3.8.4 Operational description Set up bank value and bank use in bank setting-register of each local area of LOCAL register in common area. Moreover, in that case, a combination pin is set up and mapping is simultaneously set up by the CS/WAIT controller.
Page 118 TMP91C815 Data/Stack RAM SRAM /CS0 8Mbyte 000000H〜1FFFFFH (logical) 8bit 000000H〜7FFFFFH (physical) /CS0 Optional ROM /CS1 /CS1 FLASH 400000H〜 7FFFFFH (logical) 16Mbyte 000000H〜 FFFFFFH (physical) 16bit Data Address TMP91C815 /RD,(/WR,/HWR:SRAM) Program ROM /CS2 MROM C00000H〜FFFFFFH (logical) 16Mbyte 000000H〜FFFFFFH (physical) 16bit /CS2 Data ROM EA24,EA25 /CS3...
Page 119 TMP91C815 ;Initial Setting ;CS0 (MSAR0),00H ; Logical address area: 000000H〜1FFFFFH (MAMR0),FFH ; Logical address size: 2Mbyte (B0CS),89H ; Condition: 8bit,1wait (8MB, SRAM) ;CS1 (MSAR1),40H ; Logical address area: 400000H〜7FFFFFH (MAMR1),7FH ; Logical address size: 4Mbyte (B1CS),80H ; Condition: 16bit,2wait (16Mbyte, Flash ROM) ;CS2 (MSAR2),C0H ;...
Page 120 TMP91C815 ;Bank Operation ;***** /CS2 ***** 000000H ; Program ROM: Start address at Bank0 of Local2 200000H ; Program ROM: Start address at Bank1 of Local2 400000H ; Program ROM: Start address at Bank2 of Local2 600000H ; Program ROM: Start address at Bank3 of Local2 800000H ;...
Page 121 TMP91C815 ;Bank Operation ;***** /CS2 ***** 000000H ; Program ROM: Start address at Bank0 of Local2 200000H ; Program ROM: Start address at Bank1 of Local2 ; Operation at Bank1of Local2 〜 E00100H ; Jump to Bank7(=Common2) of Local2 400000H ;...
Page 122 TMP91C815 At Figure 3.8.4.4, it shows example of program jump. In the same way with before example, two dot line squares show each /CS2’s program ROM and /CS1’s option ROM. Program start from E00000H common address, firstly, write to BANK register of LOCAL2 area upper 3-bit address of jumping point.
Page 123: Serial Channel
TMP91C815 Serial Channels TMP91C815 includes 2 serial I/O channels. For both channels either UART Mode (asynchronous transmission) or I/O Interface Mode (synchronous transmission) can be selected. • I/O Interface Mode Mode 0: For transmitting and receiving I/O data using the synchronizing signal SCLK for extending I/O.
Page 124 TMP91C815 • Mode 0 (I/O Interface Mode) bit 0 Transfer direction • Mode 1 (7-Bit UART Mode) No parity start bit 0 stop Parity start bit 0 parity stop • Mode 2 (8-Bit UART Mode) start bit 0 stop No parity start parity stop...
Page 125 TMP91C815 3.9.1 Block diagrams Figure 3.9.2 is a block diagram representing Serial Channel 0. prescaler φT0 16 32 64 φT2 φT8 φT32 Serial clock generation circuit BR0CR TA0TRG <BR0CK1, 0> (from TMRA0) BR0CR BR0ADD <BR0S3 to 0> <BR0K3 to 0> φ...
Page 126 TMP91C815 prescaler φT0 16 32 64 φT2 φT8 φT32 Serial clock generation circuit BR1CR TA0TRG <BR1CK1, BR1CK0> (from TMRA0) BR1CR BR1ADD <BR1S3 to <BR1K3 to BR1S0> BR1K0> φ UART φ Mode SIOCLK φ φ BR1CR <BR1ADDE> SC1MOD0 SC1MOD0 Baud rate <SC1, SC0>...
Page 127 TMP91C815 3.9.2 Operation of each circuit (1) Prescaler There is a 6-bit prescaler for generating a clock to SIO0. The clock selected using SYSCR<PRCK1:PRCK0> is divided by 4 and input to the prescaler as PHI_T0. The prescaler can be run by selecting the baud rate generator as the serial transfer clock. Table 3.9.2 shows prescaler clock resolution into the baud rate generator.
Page 128 TMP91C815 (2) Baud rate generator The baud rate generator is a circuit which generates transmission and receiving clocks which determine the transfer rate of the serial channels. The input clock to the baud rate generator, φT0, φT2, φT8 or φT32, is generated by the 6-bit prescaler which is shared by the timers.
Page 129 TMP91C815 • Integer divider (N divider) For example, when the source clock frequency (fc) = 12.288 MHz, the input clock frequency =PHI_T2 (fc/16), the frequency divider N (BR0CR<BR0S3 to BR0S0>) = 5, and BR0CR<BR0ADDE> = 0, the baud rate in UART Mode is as follows: ∗...
Page 130 TMP91C815 Table 3.9.3 Transfer rate selection (when baud rate generator Is used and BR0CR <BR0ADDE> = 0) Unit (kbps) Input Clock φT0 φT2 φT8 φT32 fc [MHz] Frequency Divider 76.800 19.200 4.800 1.200 38.400 9.600 2.400 0.600 9.830400 19.200 4.800 1.200 0.300 9.600...
Page 131 TMP91C815 (3) Serial clock generation circuit This circuit generates the basic clock for transmitting and receiving data. • In I/O Interface Mode In SCLK Output Mode with the setting SC0CR<IOC> = 0, the basic clock is generated by dividing the output of the baud rate generator by 2, as described previously. In SCLK Input Mode with the setting SC0CR<IOC>...
Page 132 TMP91C815 (6) The Receiving Buffers To prevent Overrun errors, the Receiving Buffers are arranged in a double-buffer structure. Received data is stored one bit at a time in Receiving Buffer 1 (which is a shift register). When 7 or 8 bits of data have been stored in Receiving Buffer 1, the stored data is transferred to Receiving Buffer 2 (SC0BUF);...
Page 133 TMP91C815 Handshake function Serial Channels 0, 1 each has a CTS pin. Use of this pin allows data can be sent in units of one frame; thus, Overrun errors can be avoided. The handshake functions is enabled or disabled by the SC0MOD <CTSE>...
Page 134 TMP91C815 (9) Transmission Buffer The Transmission Buffer (SC0BUF) shifts out and sends the transmission data written from the CPU form the least significant bit (LSB) in order. When all the bits are shifted out, the Transmission Buffer becomes empty and generates an INTTX0 interrupt. (10) Parity control circuit When SC0CR<PE>...
Page 135 TMP91C815 (12) Timing generation # In UART Mode Receiving 8-Bit + Parity (Note) Mode 9-Bit 8-Bit, 7-Bit + Parity, 7-Bit (Note) Interrupt timing Center of last bit Center of last bit Center of stop bit (bit 8) (parity bit) Framing error timing Center of stop bit Center of stop bit Center of stop bit...
Page 136 TMP91C815 3.9.3 Bit symbol CTSE SC0MOD0 Read/Write (0202H) After Reset Transfer Hand shake Receive Wake up Serial Transmission Serial transmission clock data bit 8 function function Mode (UART) 0: CTS 00: I/O interface Mode 00: TMRA0 trigger disable 0: Receive 0: disable 01: 7-bit UART Mode 01: Baud rate...
Page 137 TMP91C815 Bit symbol CTSE SC0MOD0 Read/Write (020AH) After Reset Transfer Hand shake Receive Wake up Serial Transmission Serial transmission clock data bit 8 function function Mode (UART) 0: CTS 00: I/O interface Mode 00: TMRA0 trigger disable 0: Receive 0: disable 01: 7-bit UART Mode 01: Baud rate 1: CTS...
Page 138 TMP91C815 bit Symbol EVEN OERR PERR FERR SCLKS SC0CR Read/Write R(cleared to 0 when read) (0201H) After Reset Received Parity Parity 0: SCLK0 0: baud rate data bit 8 0: odd addition 1: error generator 1: even 0: disable 1: SCLK0 Function 1: enable pin input...
Page 139 TMP91C815 bit symbol EVEN OERR PERR FERR SCLKS SC1CR Read/W rite R (cleared to 0 when) (0209H) After Reset Received Parity Parity 0: SCLK1 0: baud rate data bit 8 0: odd addition 1: error generator 1: even 0: disable 1: SCLK1 pin 1: enable Function...
Page 140 TMP91C815 Bit symbol BR0ADDE BR0CK1 BR0CK0 BR0S3 BR0S2 BR0S1 BR0S0 BR0CR Read/Write (0203H) After Reset +(16−K)/16 00: φT0 Always 01: φT2 write “0” division 10: φT8 0: Disable Setting of the Divided frequency Function 11: φT32 1: Enable +(16−K)/16 division enable Setting the input clock of baud rate generator Internal clock φT0 Disable...
Page 141 TMP91C815 − bit Symbol BR1ADDE BR1CK1 BR1CK0 BR1S3 BR1S2 BR1S1 BR1S0 BR1CR Read/Write (020BH) After reset 00: φT0 Always +(16−K)/16 01: φT2 write “0” division 10: φT8 0: Disable Divided Frequency setting Function 1: Enable 11:φT32 Input clock selection for baud rate generator +(16 - K) / 16 division enable Internal clock φT0 Disabled...
Page 142 TMP91C815 (Transmission) SC0BUF (0200H) (Reveiving) (note): Prohibit read modify write for SC0BUF. Figure 3.9.13 Serial Transmission/Receiving Buffer Registers (SIO0, SC0BUF) Bit symbol I2S0 FDPX0 SC0MOD1 (0205H) Read/Write After Reset IDLE2 duplex Function 0: Stop 0: half 1: Run 1: full Figure 3.9.14 Serial Mode Control Register 1 (SIO0, SC0MOD1) 91C815-...
Page 143 TMP91C815 (Transmission) SC1BUF (0208H) (Receiving) (note): Prohibit read modify write for SC1BUF. Figure 3.9.15 Serial Transmission/Receiving Buffer Registers (SIO1, SC1BUF) bit Symbol I2S0 FDPX0 SC1MOD1 (020DH) Read/Write After Reset IDLE2 duplex Function 0: Stop 0: half 1: Run 1: full Figure 3.9.16 Serial Mode Control Register 1 (SIO1, SC1MOD1) 91C815-140...
Page 144 TMP91C815 3.9.4 Operation in each mode (1) Mode 0 (I/O Interface Mode) This mode allows an increase in the number of I/O pins available for transmitting data to or receiving data from an external shift register. This mode includes the SCLK output mode to output synchronous clock SCLK and SCLK input mode to input external synchronous clock SCLK.
Page 145 TMP91C815 Transmission In SCLK output mode 8-bit data and a synchronous clock are output on the TXD0 and SCLK0 pins respectively each time the CPU writes the data to the Transmission Buffer. When all data is output, INTES0 <ITX0C> will be set to generate the INTTX0 interrupt. Timing to write transmisison data SCLK0 output...
Page 146 TMP91C815 In SCLK input mode, the data is shifted to Receiving Buffer 1 when the SCLK input becomes active after the receive Interrupt flag INTES0 <IRX0C> is cleared by reading the received data. When 8-bit data is received, the data will be shifted to Receiving Buffer 2 (SC0BUF according to the timing shown below) and INTES0 <IRX0C>...
Page 147 TMP91C815 (2) Mode 1 (7-bit UART Mode) 7-Bit UART Mode is selected by setting Serial Channel Mode Register SC0MOD0<SM1, SM0> to 01. In this mode, a parity bit can be added. Use of a parity bit is enabled or disabled by the setting of the Serial Channel Control Register SC0CR<PE>...
Page 148 TMP91C815 * Clock state System clock: High frequency (fc) Clock gear: 1 (fc) Prescaler clock: System clock Main settings 7 6 5 4 3 2 1 0 ← − − − − − − 0 − PCCR Set PC1 to function as the RXD0 pin. SC0MOD ←...
Page 149 TMP91C815 Protocol Select 9-Bit UART Mode on the master and slave controllers. " Set the SC0MOD0<WU> bit on each slave controller to 1 to enable data receiving. The master controller transmits one-frame data including the 8-bit select code for the slave controllers.
Page 150 TMP91C815 Setting example: To link two slave controllers serially with the master controller using the internal clock f as the transfer clock. Master Slave 1 Slave 2 Select code Select code 00000001 00001010 Since Serial Channels 0 and 1 operate in exactly the same way, Channel 0 only is used for the purposes of this explanation.
Page 151 TMP91C815 3.9.5 Support for IrDA SIO0 includes support for the IrDA 1.0 infrared data communication specification. Figure 3.9.24 shows the block diagram. Transmisison data TXD0 IR modulator IR transmitter & LED IR output SIO0 Modem Receive data RXD0 IR demodulator IR receiver IR input TMP91C815...
Page 152 3/16 pulse width when baud rate is 115.2 kbps). The TMP91C815F has the function selects the pulse width on the transmission either 3/16 or 1/16. But 1/16 pulse width can be selected when the baud rate is equal or less than 38.4 kbps only. When 57.6 kbps and 115.2 kbps, the output pulse width should not be set to T x 1/16.
Page 153 TMP91C815 As the same reason, + (16-k)/16 division function in the baud rate generator of SIO0 can not be used to generate 115.2 kbps baud rate. Also when the 38.4 kbps and 1/16 pulse width, + (16-k)/16 division function can not be used. Table 3.9.6 shows Baud rate and pulse width for (16 –...
Page 154 TMP91C815 Bit symbol PLSEL RXSEL TXEN RXEN SIRWD3 SIRWD2 SIRWD1 SIRWD0 SIRCR (0207H) Read/Write After reset Select Receive Transmit Receive Select receive pulse width Set effective pulse width for equal or more than 2x × x transmit data 0: disable 0: disable (value + 1) pulse width...
Page 155: Serial Bus Interface
TMP91C815 3.10 Serial Bus Interface (SBI) The TMP91C815F has a 1-channel serial bus interface which employs a clocked-synchronous 8-bit SIO mode and an I C bus mode. The serial bus interface is connected to an external device through P71 (SDA) and P72 (SCL) in the I C bus mode;...
Page 156 TMP91C815 3.10.2 Serial Bus Interface (SBI) Control The following registers are used to control the serial bus interface and monitor the operation status. • Serial bus interface control register 1 (SBI0CR1) • Serial bus interface control register 2 (SBI0CR2) • Serial bus interface data buffer register (SBI0DBR) •...
Page 157 TMP91C815 3.10.4 C Bus Mode Control The following registers are used to control and monitor the operation status when using the serial bus interface (SBI) in the I C bus mode. Seirial Bus Interface Conrol Register 1 SCK0/ Bit symbol SCK2 SCK1 SBI0CR1...
Page 158 TMP91C815 Serial Bus Interface Control Register 2 Bit symbol SBIM1 SBIM0 SWRST1 SWRST0 SBI0CR2 (0243H) Read/Write W (Note 1) W (Note 1) After Reset Master/Slave Transmitter/ Start/Stop Cancel Serial bus interface operating Software reset generate write Prohibit selection Receiver generation INTSBI mode selection (note 2) “10”...
Page 159 TMP91C815 Serial Bus Interface Status Register bit Symbol SBI0SR (0243H) Read/Write After reset Master/ Transmitter/ C bus INTSBI2 Arbitration Slave GENERAL Last Prohibit Slave Receiver status interrupt lost address CALL received bit Read- status status monitor request detection match detection monitor modify-write monitor...
Page 160 TMP91C815 Serial Bus Interface Baud Rate Regster 0 bit Symbol I2SBI0 SBI0BR0 (0244H) Read/Write After Reset Allways ‘0’ IDLE2 write 0: Stop Function 1: Run Operation during IDLE 2 Mode Stop Operation Serial Bus Interface Baud Rate Register 1 Bit symbol P4EN SBI0BR1 (0245H)
Page 161 In the receiver mode during the clock pulse cycle, the SDA pin is set to the Low in order to generate the acknowledge signal. Clear the <ACK> to 0 for operation in the Non-Acknowledge Mode, The TMP91C815F does not generate a clock pulse for the Acknowledge signal when operating in the Master Mode, and it does not count a clock pulse as an Acknowledge signal when operating in Slave Mode.
Page 162 Low-level width from among those master devices connected to the bus. (4) Slave address and address recognition mode specification When the TMP91C815F is used as a slave device, set the slave address <SA6 to SA0> and <ALS> to the I2C0AR. Clear the <ALS> to “0” for the address recognition mode.
Page 163 TMP91C815 (6) Transmitter/Receiver selection Set the SBI0CR2<TRX> to “1” for operating the TMP91C815F as a transmitter. Clear the <TRX> to “0” for operation as a receiver. When data with an addressing format is transferred in Slave Mode, when a slave address with the same value that an I2C0AR or a GENERAL CALL is received (all 8-bit data are “0”...
Page 164 TMP91C815 Interrupt service requests and interrupt cancellation When a serial bus interface interrupt request (INTS2) occurs, the SBI0CR2 <PIN> is cleared to “0”. During the time that the SBI0CR2<PIN> is “0”, the SCL line is pulled down to the Low level. The <PIN>...
Page 165 TMP91C815 The TMP91C815F compares the levels on the bus’s SDA line with those of the internal SDA output on the rising edge of the SCL line. If the levels do not match, arbitration is lost and SBI0SR<AL> is set to “1”.
Page 166 (16) I CBUS Address Register (I2C0AR) I2C0AR<SA6 to SA0> is used to set the slave address when the TMP91C815F functions as a slave device. The slave address output from the master device is recognized by setting the I2C0AR<ALS> to “0”.
Page 167 TMP91C815 3.10.6 Data Transfer in I C Bus Mode (1) Device initialization Set the SBI0BR1<P4EN>, SBI0CR1<ACK,SCK2 to SCK0>, Set SBI0BR1 to “1” and clear bits 7 to 5 and 3 in the SBI0CR1 to “0”. Set a slave address <SA6 to SA0> and the <ALS> (<ALS> = “0” when an addressing format) to the I2C0AR.
Page 168 TMP91C815 SCL line SDA line Acknowledge Slave address + derection bit signal from a Start condtion slave device <PIN> INTS2 interrupt request output of Master output of Slave Figure 3.10.13 Start Condition Generation and Slave Address Transfer (3) 1-word Data Transfer Check the <MST>...
Page 169 An INTS2 interrupt request then occurs and the <PIN> becomes “0”, Then the TMP91C815F pulls down the SCL pin to the Low-level. The TMP91C815F outputs a clock pulse for 1-word of data transfer and the acknowledge signal each time that received data is read from the SBI0DBR.
Page 170 / writing from / to the SBI0DBR or setting the <PIN> to “1” will release the SCL pin after taking time. In the slave mode the TMP91C815F operates either in normal slave mode or in slave mode after losing arbitration.
Page 171 TMP91C815 (4) Stop condition generation When SBI0SR<BB> = 1, the sequence for generating a stop condition can be initiated by writing “1” to SBI0CR2<MST,TRX,PIN> and “0” to SBI0CR2<BB>. Do not modify the contents of SBI0CR2<MST,TRX,PIN,BB> until a stop condition has been generated on the bus. When the bus’s SCL line has been pulled Low by another device, the TMP91C815 generates a stop condition when the other device has released the SCL line.
Page 172 0 → <TRX> 1 → <TRX> 0 → <BB> 1 → <BB> 1 → <PIN> 1 → <PIN> 4.7[µs] (Min.) Start codnition SCL line Internal SCL output (TMP91C815) SDA line <LRB> <BB> <PIN> Figure 3.10.19 Timing diagram for TMP91C815F Restart 91C815-...
Page 173 TMP91C815 3.10.7 Clocked Synchronous 8-Bit SIO Mode control The following registers are used to control and monitor the operation status when the Serial Bus Interface (SBI) is being operated in Clocked Synchronous 8-Bit SIO Mode. S erial Bus Interfac e C ontrol R egister 1 SCK0/ Bit s ymbol SIOS...
Page 174 TMP91C815 91C815-...
Page 175 TMP91C815 Serial Bus Interface Control Register 2 Bit symbol SBIM1 SBIM0 SBI0CR2 (0243H) Read/Write After Reset Serial bus interface operation Prohibit mode selection Read- 00: Port mode modify-write Function 01: SIO mode 10: I C bus mode 11: (reserved) Serial bus interface operation mode selection 00 Port Mode (serial bus interface output disabled) 01 Clocked-Synchronous 8-Bit SIO Mode 10 I...
Page 176 TMP91C815 Serial Bus Interface Baud Rate Register 0 Bit symbol I2SBI0 SBI0BR0 (0244H) Read/Write After Reset Allways ‘0’ IDLE2 write 0: STOP Function 1: RUN Operation in IDLE 2 Mode Stop Operate Serial Bus Interface Baud Rate Register 1 Bit symbol P4EN SBI0BR1 (0245H)
Page 177 TMP91C815 (1) Serial Clock Clock source SBI0CR1<SCK2 to SCK0> is used to select the following functions: Internal Clock In Internal Clock Mode one of seven frequencies can be selected. The serial clock signal is output to the outside on the SCK pin. The SCK pin goes High when data transfer starts. When the device is writing (in Transmit Mode) or reading (in Receive Mode), data cannot follow the serial clock rate, so an automatic wait function is executed which automatically stops the serial clock and holds the next shift operation until reading or writing has been completed.
Page 178 TMP91C815 Shift edge Data is transmitted on the leading edge of the clock and received on the trailing edge. Leading edge shift Data is shifted on the leading edge of the serial clock (on the falling edge of the SCK pin input/output).
Page 179 TMP91C815 (2) Transfer modes The SBI0CR1<SIOM1 to SIOM0> is used to select a transmit, receive or transmit / receive mode. 8-Bit Transmit Mode Set a control register to a transmit mode and write transmit data to the SBI0DBR. After the transmit data is written, set the SBI0CR1<SIOS> to “1” to start data transfer. The transmitted data is transferred from SBI0DBR to the Shift Register and output to the SO pin in synchronized with the serial clock, starting from the least significant bit (LSB), When the transmission data is transferred to the Shift Register, the SBI0DBR becomes empty.
Page 180 TMP91C815 Example: Program to stop data transmission (when an external clock is used) Clear<SIOS> <SIOS> <SIOF> <SEF> SCK pin (output) SO pin INTSBI interrupt request SBI0DBR (a) Internal clock Write transmitted data Clear <SIOS> <SIOS> <SIOF> <SEF> SCK pin (input) SO pin INTSBI interrupt request...
Page 181 TMP91C815 8-Bit Receive Mode SCK pin SIOF SO pin bit 6 bit 7 = Min. 3.5/f SODH Figure 3.10.27 Transmitted data hold time at end of transmission Set the control register to receive mode and set SBI0CR1<SIOS> to “1” for switching to receive mode.
Page 182 TMP91C815 Clear <SIOS> <SIOS> <SIOF> <SEF> SCK pin (output) SI pin INTS2 interrupt request SBI0DBR Read receiver data Read receiver data Figure 3.10.28 Receiver Mode (example: Internal clock) 8-Bit Transmit/Receive Mode Set a control register to a transmit/receive mode and write data to SBI0DBR. After the data has been written, set SBI0CR<SIOS>...
Page 183 TMP91C815 Clear <SIOS> <SIOS> <SIOF> <SEF> SCK pin (output) SO pin SI pin INTSBI interrupt request SBI0DBR Write transmitted Read received Write transmitted Read received data (a) data (c) data (b) data (d) Figure 3.10.29 Transmit/Received Mode (example using internal clock) SCK pin SIOF SO pin...
Page 184: Analog/Digital Converter
TMP91C815 3.11 Analog/Digital Converter The TMP91C815 incorporates a 10-bit successive approximation-type analog/digital converter (A/D converter) with 8-channel analog input. Figure 3.11.1 is a block diagram of the A/D converter. The 8-channel analog input pins (AN0 to AN7) are shared with the input-only port 8 and can thus be used as an input port. (note): When IDLE2, IDLE1 or STOP mode is selected, so as to reduce the power, with some timings the system may enter a stand-by mode even though the internal comparator is still enabled.
Page 185 TMP91C815 3.11.1 Analog/Digital converter registers The A/D converter is controlled by the two A/D mode control registers: ADMOD0 and ADMOD1. The A/D conversion results are stored in 8 kinds of A/D conversion data Upper and Lower registers: ADREG04H/L, ADREG15H/L, ADREG26H/L and ADREG37H/L. Figure 3.11.2 shows the registers related to the A/D converter.
Page 186 TMP91C815 A/D Mode Control Register 1 Bit symbol VREFON I2AD ADTRGE ADCH2 ADCH1 ADCH0 ADMOD1 (02B1H) Read/Write After Reset VREF IDLE2 A/D external Analog input channel selection application 0: Stop trigger start Function control 1: Operate control 0: OFF 0: disable 1: ON 1: enable Analog input channel selection...
Page 187 TMP91C815 A/D Conversion Data Low Register 0/4 Bit symbol ADR01 ADR00 ADR0RF ADREG04L (02A0H) Read/Write After Reset Undefined Function Stores lower 2-bits of Conversion A/D conversion result Data Storage flag 1: Conversion result stored A/D Conversion Data Upper Register 0/4 Bit symbol ADR09 ADR08...
Page 188 TMP91C815 A/D Conversion Result Lower Register 2/6 Bit symbol ADR21 ADR20 ADR2RF ADREG26L (02A4H) Read/Write After Reset Undefined Stores lower 2-bits of conversion A/D conversion result. data storage Function flag 1: Conversion result stored A/D Conversion Data upper Register 2/6 Bit symbol ADR29 ADR28...
Page 189 TMP91C815 3.11.2 Description of operation (1) Analog reference voltage A High-level analog reference voltage is applied to the VREFH pin; a low-level analog reference voltage is applied to the VREFL pin. To perform A/D conversion, the reference voltage as the difference between VREFH and VREFL, is divided by 1024 using string resistance.
Page 190 TMP91C815 (3) Starting A/D Conversion To start A/D conversion, write “1” to ADMOD0<ADS> in A/D Mode Control Register 0, or ADMOD1<ADTRGE> in A/D Mode Control Register 1 and input falling edge on ADTRG pin. When A/D conversion starts, the A/D Conversion Busy flag ADMOD0<ADBF> will be set to “1”, indicating that A/D conversion is in progress.
Page 191 TMP91C815 ③ Channel Fixed Repeat Conversion Mode Setting ADMOD0<REPET> and ADMOD0<SCAN> to “10” selects Channel Fixed Repeat Conversion Mode. In this mode, data on one specified channel is converted repeatedly. When conversion has been completed, ADMOD0<EOCF> is set to “1” and ADMOD0<ADBF> is not cleared to “0” but held “1”.
Page 192 TMP91C815 (5) A/D conversion time 84 states (10.5 µs @ f = 16MHz) are required for the A/D conversion for one channel. (6) Storing and reading the results of A/D conversion The A/D Conversion Data Upper and Lower Registers (ADREG04H/L to ADREG37H/L) store the A/D conversion results.
Page 193 TMP91C815 Setting example: ① Convert the analog input voltage on the AN3 pin and write the result, to memory address 0800H using the A/D interrupt (INTAD) processing routine. Main routine: 7 6 5 4 3 2 1 0 ← X 1 0 0 - - - - INTE0AD Enable INTAD and set it to Interrupt Level 4.
Page 194: Watch Dog Timer
TMP91C815 3.12 Watch Dog Timer (runaway detection timer) The TMP91C815 features a watch dog timer for detecting runaway. The watch dog timer (WDT) is used to return the CPU to normal state when it detects that the CPU has started to malfunction (runaway) due to causes such as noise.
Page 195 TMP91C815 The watch dog timer consists of a 22-stage binary counter which uses the system clock (f ) as the input clock. The binary counter can output f /215, f /217, f /219 and /221. Selecting one of the fSYS outputs using WDMOD<WDTP1,WDTP0>...
Page 196 TMP91C815 3.12.2 Control registers The watchdog timer WDT is controlled by two control registers WDMOD and WDCR. (1) Watch dog timer Mode Register (WDMOD) Setting the detection time for the watch dog timer in <WDTP1,WDTP0> This 2-bit register is used for setting the watch dog timer interrupt time used when detecting runaway.
Page 197 TMP91C815 − Bit symbol WDTE WDTP1 WDTP0 I2WDT RESCR Read/Write WDMOD After Reset (0300H) Select detecting time IDLE2 1: Internally Always control 00: 2 0: Stop connects write “0” 1: enable 01: 2 1: Operate WDL out Function to the 10: 2 reset pin 11: 2...
Page 198 TMP91C815 − Bit symbol WDCR Read/Write (0301H) − After reset B1H: WDT disable code Function 4EH: WDT clear code Disable/Clear WDT Disable code Clear code Others Don’t care Figure 3.12.5 Watch dog timer control register 91C815-...
Page 199 TMP91C815 3.12.3 Operation The watch dog timer generates an INTWD interrupt when the detection time set in the WDMOD<WDTP1,WDTP0> has elapsed. The watch dog timer must be cleared “0” by software before an INTWD interrupt will be generated. If the CPU malfunctions (i.e. if runaway occurs) due to causes such as noise, but does not execute the instruction used to clear the binary counter, the binary counter will overflow and an INTWD interrupt will be generated.
Page 200 TMP91C815 3.13 Real time clock (RTC) 3.13.1 Function description for RTC Clock function (hour , minute , second) Calendar function (month and day , day of the week , and leap year) 24 or 12-hour (AM/PM) clock function ± 30 second adjustment function (by software) Alarm function (Alarm output) Alarm interrupt generate 3.13.2 Block diagram...
Page 201 TMP91C815 3.13.3 Control registers Table 3.13(1) PAGE 0 (Timer function) registers Read/Writ Symbol Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 Bit0 Function SECR 0320h Second column 40 sec. 20 sec. 10 sec. 8 sec. 4 sec. 2 sec. 1 sec MINR 0321h 8 min.
Page 202 TMP91C815 3.13.4 Detailed explanation of control register RTC is not initialized by reset. Therefore, all registers must be initialized at the beginning of the program. (1) Second column register (for PAGE0 only) SECR bit Symbol (0320H) Read/Write After reset Undefined "0"...
Page 203 TMP91C815 (2) Minute column register (for PAGE0/1) MINR bit Symbol (0321H) Read/Write After reset Undefined "0" is 40 min, 20min, 10min, 8 min. 4 min. 2 min, 1min, Function read. column column column column column column column 0 min. 1 min. 2 min.
Page 204 TMP91C815 (3) Hour column register (for PAGE0/1) ① In case of 24-hour clock mode (MONTHR<MO0>=’1’) of PAGE1 HOURR bit Symbol (0322H) Read/Write After reset Undefined 20 hour 10 hour 8 hour 4 hour 2 hour 1 hour "0" is read. Function column column...
Page 205 TMP91C815 (4) Day of the week column register (for PAGE0/1) DAYR bit Symbol (0323H) Read/Write After reset Undefined Function "0" is read. Sunday Monday Tuesday Wednesday Thursday Friday Saturday (5) Day column register (for PAGE0/1) DATER bit Symbol (0324H) Read/Write After reset Undefined Function...
Page 206 TMP91C815 (6) Month column register (for PAGE0 only) MONTHR bit Symbol (0325H) Read/Write After reset Undefined Function "0" is read. 10 months 8 months 4 months 2 months 1 month January February March April June July August September October November December (7) Select 24-hour clock or 12-hour clock (for PAGE1 only) MONTHR...
Page 207 TMP91C815 (8) Year column register (for PAGE0 only) YEARR bit Symbol (0326H) Read/Write After reset Undefined 80 Years Function 40 Years 20 Years 10 Years 8 Years 4 Years 2 Years 1 Year 99 year 00 year 01 year 02 year 03 year 04 year 05 year...
Page 208 TMP91C815 (10) PAGE register setting (for PAGE0/1) PAGER bit Symbol INTENA PAGE ADJUST ENATMR ENAALM (0327H) Read/Write ― After reset Undefined Undefined Note: TIMER ALARM "0" is PAGE Interrupt Function "0" is read. 1:ADJUST 1:ENABLE 1:ENABLE 1:ENABLE read. select 0:DISABLE 0:DISABLE 0:DISABLE Prohibit Read Modify Write...
Page 209 TMP91C815 3.13.5 Operational description (1) Reading timer data ① There is the case which reads wrong data when carry of the inside counter happens during the operation which timer data reads. Therefore, please read two times with the following way for reading correct data. START PAGER<PA0>=’0’, Select PAGE0 ...
Page 210 TMP91C815 ② Readout of timer data that used /ALARM output Timer data can be read with rising edge of /ALARM output by detecting /ALARM='1' with interrupt routine of INTRTC of 1 Hz START RESTR<DIS1HZ>=’0’, RESTR<DIS16HZ>=’1’, PAGER<ENAALM>=’0’ Enable 1Hz output INTRTC? (1Hz) /ALARM=1? (note):...
Page 211 TMP91C815 (2) Writing timer data When there is carry on the way of write operation , expecting data can not be wrote exactly. Therefore, in order to write in data exactly please follow the below way. ① Reset for a divider Inside of RTC, there is 15-stage divider which generates 1Hz clock from 32,768KHz.
Page 212 TMP91C815 ② Disabling the timer Carry of a timer is prohibited when write '0' to PAGER<ENATMR> and can prevent malfunction by CLOCK HOLD circuit. During a timer prohibited, CLOCK HOLD circuit holds one sec. carry signal which is generated from divider. After becoming timer enable state, output the carry signal to timer and revise time and continue operation.
Page 213 TMP91C815 Explanation of the alarm function Can use alarm function by setting of register of PAGE1 and output either of three signal from /ALARM pin as follows. (1) In accordance of alarm register and the timer, output '0'. (2) Output clock of 1Hz. (3) Output clock of 16Hz.
Page 214 TMP91C815 3.14 LCD driver controller (LCDC) The TMP91C815F incorporates two types liquid crystal display driving circuit for controlling LCD driver LSI. One circuit handles a RAM build-in type LCD driver that can store display data in the LCD driver in itself, and the other circuit handles a shift-register type LCD driver that must serially transfer the display data to LCD driver for each display picture.
Page 215 TMP91C815 3.14.1 Feature of LCDC of each mode Each feature and operation of pin is as follows. Table 3.14.1 Feature of LCDC of each mode Shift- register type LCD driver RAM built-in type LCD driver control mode control mode Common(row):64,68,80,100,120, The number of picture 128,144,160,200,240 There is not a limitation...
Page 216 TMP91C815 3.14.2 Block Diagram Selector CPU address bus :A0〜23 A0〜A23 LCDSAH/L Lower address register(10bit) Increm ent (14bit) Internal clear data bus D0〜D7 Latch, shifter SCPEN& /RD RD,<BUS1:0> System clock D1BSCP generate CPU BUSAK SR,<BUS1:0> Output Counter (9bit) SEG END Com parater BUSRQ SEG register SCPEN...
Page 217 TMP91C815 3.14.3 Control registers LCDSAL Register LCDSAL bit Symbol SAL15 SAL14 SAL13 SAL12 MODE (0360H) Read/Write After reset SR mode Always Always Mode Display memory address (Low: A15 to A12) write 0 write 0 select Function 0: RAM 1: SR LCDSAH Register LCDSAH bit Symbol...
Page 218 Function Depend on the specification of external LCD driver These registers do not exist on TMP91C815F. These are image for instruction registers and display registers of external RAM built-in sequential access type LCD driver. Address as table 3.14.2 is assigned to these registers, and the following chip enable pin becomes active when accesses corresponding address.
Page 219 TMP91C815 table 3.14.2 Memory mapping for built-in RAM sequential access type. Register Address Purpose Chip enable terminal Sequential access type terminal RAM built-in type Instruction LCDC1L 0FE0H D1BSCP driver 1 Display data LCDC1H 0FE1H RAM built-in type Instruction LCDC2L 0FE2H D2BLP driver 2 Display data...
Page 220 TMP91C815 3.14.4 Shift- register type LCD driver control mode (SR mode) Set the mode of operation, start address of source data save memory and LCD size to control registers before setting start register. After set start register LCDC outputs bus release request to CPU and read data from source memory. After that LCDC transmits data of volume of LCD size to external LCD driver through data bus .
Page 221 TMP91C815 Settlement of Frame frequency function 3.14.4.1 TMP91C815 defines so-called frame period (refresh interval for LCD panel) by the value set in fFP[8:0] . DLEBCD pin outputs pulse every frame period. DLEBFR pin usually outputs the signal inverts polarity every frame period.
Page 222 TMP91C815 3.14.4.2 Timer Out LCDCK LCD source clock (LCDCK) can select low frequency (XT1,XT2 :32.768[KHz]) or timer out (TA3OUT) outputs from internal TMRA23. (EX.2) : Here indicates the method that frame period is set 70[Hz] by selecting TA3OUT for source clock of LCD .(fc = 6[MHz] , 120COM) The next equation calculates frame period.
Page 223 TMP91C815 =78.02Hz (@<FP1:0>=00) D3BFR 1 picture (120com) display time DLEBCD D2BLP D1BSCP D7-D0 Data transmission (240seg=30 byte) of volume of 1com figure 3.14.2 Timing diagram for SR mode D3BFR : LP period DLEBCD :stop time : CPU operating time STOP D2BLP =0.5XT BUSRQ(internal)
Page 224 TMP91C815 table 3.14.4 Performance listing for each segment and common number unit XT number of counts for tLP making: D 198.4 183.1 152.6 122.1 106.8 91.6 76.3 76.3 61.0 45.8 STOP 32seg CPU stop rate STOP 64seg CPU stop rate STOP 80seg CPU stop rate...
Page 225 TMP91C815 table 3.14.5 f table for each common number. (1/2) 80 100 120 128 144 160 200 240 COM+0 78.77 80.31 81.92 81.92 78.02 85.33 91.02 81.92 81.92 91.02 COM+1 77.56 79.15 80.91 81.11 77.37 84.67 90.39 81.41 81.51 90.64 76.38 78.02 79.92...
Page 226 TMP91C815 fFP table for each common number. (2/2) 80 100 120 128 144 160 200 240 COM+40 48.47 50.57 54.61 58.51 58.51 65.02 71.23 65.54 68.27 78.02 48.01 50.10 54.16 58.10 58.15 64.63 70.85 65.21 67.98 77.74 47.56 49.65 53.72 57.69 57.79 64.25...
Page 227 TMP91C815 T 6C13B 91C815 (240-row driver selection) V DD O001 COM 001 240CO M × × × × 240SEG TES T Di7-Di0 DUA L VCCL/R, V 0L/R, V1L/R, V 4L/R, V5L/R O240 COM 240 DLEB CD D1BS CP D2B LP D3BFR /DOFF /DSP OF...
Page 228 TMP91C815 D0 D1 D2 D3 D4 D5 D6 D7 Segment 9 10 11 … 239 240 1000h 1001h 101dh 101eh 2c1fh Common Relation display panel and display memory (in case of above setting) 3.14.4.3 Transfer time by data bus width Data bus width of LCD driver can be selected either of BYTE/NIBBLE/BIT by LCDCTL<BUS1:0>.
Page 229 TMP91C815 P54,P55 terminal includes /BUSRQ,/BUSAK function. This terminal is used for connect external DMA controller . This function cannot be used in same time for SR mode of LCDC. 91C815-...
Page 230 TMP91C815 3.14.5 RAM built-in type LCD driver control mode (RAM mode) Data transmission to LCD driver is executed by move instruction of CPU. After setting mode of operation to control register, when move instruction of CPU is executed LCDC outputs chip select signal to LCD driver connected to the outside from control pin (D1BSCP etc.) .
Page 231 TMP91C815 T 6B66A 91C815F (65-row driver) V DD COM 001 COM 001 65CO M × × × × 80SEG VLC1,VLC2, VLC3,VLC4, VLC5 COM 065 COM065 DLEB CD D1BS CP /W R /W R /DOFF /DSP OF DB 0〜 DB 7 D0〜...
Page 232 TMP91C815 3.15 Melody / Alarm generator(MLD) TMP91C815 incorporates melody function and alarm function, both of which are output from the MLDALM pin. 5 kinds of fixed cycle interrupts are generated by the 15-bit free-run counter which is used for alarm generator. Features are as follows.
Page 233 TMP91C815 3.15.1 Block Diagram Reset Internal Data Bus [Melody Generator] MELFH,MELFLResistor MELFH <MELON> MELOUT EMCCR0 invert <TA3MCDE> Comparator(CP0) Stop&clear Low-speed clock clear (32.76hKHz) selector 12bit counter(UC0) TA3OUT INTALM0(8KHz) INTALM1(512Hz) Edge INTALM2(64Hz) ditect INTALM3(2Hz) INTALM4(1Hz) 15bit counter(UC1) INTALMH ALMINT (HALT release) <IALME4:0>...
Page 234 TMP91C815 3.15.2 Control registers ALM R register bit Symbol (0330H) Read/Write After reset Function Setting alarm pattern MLDALMC register MELALMC bit Symbol ALMINV MELALM (0331H) Read/Write After reset Free-run counter control Output Alarm 00: Hold Waveform Wavefor Write “0” select 01: Restart Function m invert...
Page 235 TMP91C815 3.15.3 Operational Description 3.15.3.1 Melody generator The Melody function generates signals of any frequency (4Hz- 5461Hz) based on low-speed clock (32.768KHz) and outputs the signals from the MLDALM pin. By connecting a loud speaker outside, Melody tone can sound easily. (Operation) At first, MELALMC<MELALM>...
Page 236 TMP91C815 3.15.3.2 Alarm generator The Alarm function generates 8 kinds of alarm waveform having a modulation frequency 4096Hz determined by the low-speed clock (32.768KHz). And this waveform is reversible by setting a value to a register. By connecting a loud speaker outside, Alarm tone can sound easily. 5 kinds of fixed cycle (1Hz,2Hz,64Hz,512Hz,8KHz) interrupts are generate by the free-run counter which is used for alarm generator.
Page 237 TMP91C815 Example: Waveform of alarm pattern for each setting value : not invert) AL1 pattern Modulation frequency(4096Hz) (Continuous output) AL2 pattern (8 times/1sec) 31.25ms 1sec AL3 pattern (once) 500ms AL4 pattern (Twice/1sec) 62.5ms 1sec AL5 pattern (3 times/1sec) 1sec 62.5ms AL6 pattern (once) 62.5ms...
Page 238 TMP91C815 Electrical Characteristics Absolute Maximum Ratings Symbol Parameter Rating Unit −0.5 to 4.0 Power Supply Voltage −0.5 to Vcc + 0.5 Input Voltage Output Current −2 Output Current ΣIOL Output Current (total) ΣIOH −80 Output Current (total) Power Dissipation (Ta = 85°C) TSOLDER Soldering Temperature (10 s) °C...
Page 239 TMP91C815 4.2 DC Characteristics (2/2) Symbol Parameter Min. Typ. Max. Unit Condition (note1) Input Leakage Current 0.02 ± 5 0.0≦VIN≦Vcc μA Output Leakage Current 0.05 ± 10 0.2≦VIN≦ Vcc-0.2 Power Down Voltage VIL2 = 0.2Vcc, VSTOP (@STOP,RAM Back up) VIH2 = 0.8Vcc 3.6V≧Vcc≧2.7V RRST RESET Pull Up Resister...
Page 240 TMP91C815 AC Characteristics (1) Vcc = 2.7〜3.6V = 27 MHz Variable No. Symbol Parameter Unit Period ( = x) 37.0 31250 37.0 x − 23 A0 to 23 Valid → RD / WR Fall 0.5x −13 RD Rise → A0 to A23 Hold x −...
Page 241 TMP91C815 (2) Vcc = 2.0 V ± 10% Variable 25 MHz Unit No. Symbol Parameter 31250 Period ( = x) tFPH x -46 A0 to A15 Valid → RD / WR Fall 0.5x - 26 tCAR RD Rise → A0 to A23 Hold x - 26 tCAW WR Rise →...
Page 242 TMP91C815 (1) Read Cycle EA24-25, A23〜0 /CSn WAIT APH2 Port Input D0∼15 D0〜15 91C815-239...
Page 243 TMP91C815 (2) Write Cycle EA24-25, A23∼0 /CSn WAIT Port Output D0∼15 D0〜15 91C815-...
Page 244 TMP91C815 A/D Conversion Characteristics AVcc = Vcc, AVss = Vss Symbol parameter Condition Typ. Unit − 0.2 V 3.6V≧Vcc≧2.7V Analog Reference Voltage ( + ) VREFH = 2 V ± 10% Vss + 0.2 V 3.6V≧Vcc≧2.7V Analog Reference Voltage ( − ) VREFL = 2 V ±...
Page 245 TMP91C815 Serial Channel Timing (I/O Internal Mode) (1) SCLK Input Mode Variable 10 MHz 27 MHz Symbol Parameter Unit µ s SCLK Period 0.59 Output Data /2 − 4X − 110 Vcc=3V±10％ → SCLK Rising/Falling /2 − 4X − 180 Vcc=2V±10％...
Page 246 TMP91C815 Event Counter (TA0IN) Variable 10 MHz 27 MHz Symbol Parameter Unit 8X + 100 Clock Period 4X + 40 Clock Low Level Width VCKL 4X + 40 Clock High Level Width VCKH Interrupt, Capture (1) NMI , INT0 to INT3 Interrupts Variable 10 MHz 27 MHz...
Page 247 TMP91C815 SCOUT Pin AC Characteristics Variable 4 MHz 16 MHz Symbol Parameter Condition Unit 0.5T − 10 Vcc ≧ 2.7 V Low level Width 0.5T − 30 Vcc ＜ 2.7 V 0.5T − 10 Vcc ≧ 2.7 V High level Width 0.5T −...
Page 248 TMP91C815 4.10 LCD CONTROL SR mode EA24-25, A23 to 0, /CSn D1BSCP D0 to 7 D0 to 7 out Variable 27MHz 10MHz Condition Unit No. symbol Parameter Max Min Max Min Max t DSU D1BSCP Fall 0.5X-8 VCC=3.0V±10% →Data Set-up 0.5X-20 VCC=2.0V±10% t DHD D1BSCP Fall...
Page 249 TMP91C815 4.11 Recommended Crystal Oscillation Circuit TMP91C815 is evaluated by below oscillator vender. When selecting external parts, make use of this information.. (note): Total loads value of oscillator is sum of external loads(C1 and C2) and floating loads of actual assemble board.
Page 250 TMP91C815 (2) TMP91C815 recommended ceramic oscillator : MURATA co. LTD; JAPAN Circuit parameter recommended Parameter of elements Running Condition Oscillation Item of Oscillator Voltage of Tc [℃] Frequency [pF] [pF] [Ω] [Ω] Power [V] [MHZ] CSTLS2M00G56-B0 (47) (47) Open 2.00M CSTLS2M50G56-B0 (47)
Page 251 TMP91C815 Table of SFRs (SFR ; special function register) The SFRs include the I/O ports and peripheral control registers allocated to the 4K bytes address space from 000000H to 000FFFH. (1) I/O Port (2) I/O Port Control (3) Interrupt Control (4) Chip Select / Wait Control (5) Clock Gear (6) DFM (Clock Doubler)
Page 252 TMP91C815 Table 5.1 Address map SFRs [1], [2] PORT Address Name Address Name Address Name 0000H 0010H 0022H 1H P1 1H PAFC 2H P6 2H PB 3H P7 3H PC 4H P1CR 4H PBCR 5H P6FC 5H PBFC 6H P2 6H P7CR 6H PCCR 7H P7FC...
Page 253 TMP91C815 Table 5.2 Address map SFRs [7] TMRA Address Name 0100H TA01RUN 2H TA0REG 3H TA1REG 4H TA01MOD 5H TA01FFCR 8H TA23RUN AH TA2REG BH TA3REG CH TA23MOD DH TA3FFCR [8] UART/SIO [9] I2CBUS/SIO Address Name Address Name 0200H SC0BUF 0240H SBI0CR1 1H SC0CR 1H SBI0DBR...
Page 254 TMP91C815 Table 5.3 Address map SFRs [11] WDT [12] RTC Address Name Address Name 0300H WDMOD 0320H SECR WDCR MINR HOURR DAYR DATER MONTHR YEWRR PAGER RESTR [13] MLD [13] MMU Address Name Address Name 0330H 0350H LOCAL0 MELALMC LOCAL1 MELFL LOCAL2 MELFH...
Page 255 TMP91C815 (1) I/O Ports Symbol Name Address PORT1 Input Mode PORT2 Input Mode Input Mode PORT5 Input Mode (Pull Up) PSRAM PORT6 PORT7 Input Mode PORT8 Input Mode PORT9 Input Mode PORTA PORTB Input Mode PORTC Input Mode PORTD 91C815-...
Page 256 TMP91C815 (2) I/O Port Control (1/2) Symbol Name Address P17C P16C P15C P14C P13C P12C P11C P10C PORT1 P1CR Control (Prohibit RWM) 0: IN 1: OUT P27F P26F P25F P24F P23F P22F P21F P20F PORT2 P2FC Function (Prohibit RWM) 0: Port, 1:Address bus (A23 to A16) P56C P55C P54C...
Page 257 TMP91C815 I/O Port Control (2/2) Symbol Name Address ODEP72 ODEP71 P7ODE PORT7 Open Drain (Prohibit 0: 3STATE RWM) 1: Open Drain P97F P96F P95F P94F P93F P92F P91F P90F PORT9 P9FC Function (Prohibit RWM) 0: KEY-IN DISABLE , 1:KEY-IN ENABLE PA7F PA6F PA5F...
Page 258 TMP91C815 Interrupt Control (1/3) Symbol Name Address INTAD INT0 Interrupt IADC IADM2 IADM1 IADM0 I0M2 I0M1 I0M0 INTE- Enable 0 & A/D Interrupt level Interrupt level 1: INTAD 1: INT0 INT2 INT1 Interrupt INTE12 I2M2 I2M1 I2M0 I1M2 I1M1 I1M0 Enable Interrupt level Interrupt level...
Page 259 TMP91C815 Interrupt Control (2/3) Symbol Name Address INTTX0 INTRX0 Interrupt ITX0C ITX0M2 ITX0M1 ITX0M0 IRX0C IRX0M2 IRX0M1 IRX0M0 INTES0 Enable Serial 0 Interrupt level Interrupt level 1: INTTX0 1: INTRX0 INTTX1 INTRX1 Interrupt ITX1C ITX1M2 ITX1M1 ITX1M0 IRX1C IRX1M2 IRX1M1 IRX1M0 INTES1 Enable...
Page 260 TMP91C815 Interrupt Control (3/3) Symbol Name Address DMA0V5 DMA0V4 DMA0V3 DMA0V2 DMA0V1 DMA0V0 DMA 0 DMA0 Request Vector DMA0 Start vector DMA1V5 DMA1V4 DMA1V3 DMA1V2 DMA1V1 DMA1V0 DMA 1 DMA1 Request Vector DMA1 Start vector DMA2V5 DMA2V4 DMA2V3 DMA2V2 DMA2V1 DMA2V0 DMA 2 DMA2...
Page 261 TMP91C815 (4) Chip Select/Wait Control (1/2) Symbol Name Address B00M1 B00M0 B0BUS B0W2 B0W1 B0W0 B0CS Block 0 CS/WAIT 0: DIS 00: ROM/SRAM Data bus 000: 2WAIT 100: Reserved control 1: EN width 001: 1WAIT 101: 3WAIT Register (Prohibit 010: 1 + NWAIT 110: 4WAIT Reserved 0: 16 bit RMW)
Page 262 TMP91C815 Chip Select/Wait Control (2/2) Symbol Name Address Memory Start MSAR2 Address Reg2 Start address A23 to A16 Memory MAMR2 Address Mask Reg2 CS0 area size 0: enable to address comparison Memory Start MSAR3 Address Reg3 Start address A23 to A16 Memory MAMR3 Address...
Page 263 TMP91C815 Clock Gear (1/2) Symbol Name Address XTEN RXEN RXTEN RSYSCK WUEF PRCK1 PRCK0 SYSCR0 System Clock Control Register High- Low- High-frequenc Low-frequenc Select clock Warm-up Select prescaler clock 00: f frequency frequency y oscillator (fc) y oscillator (fs) after release of timer oscillator (fc) oscillator (fs)
Page 264 TMP91C815 Clock Gear (2/2) Symbol Name Address EXTIN DRVOSCL PROTECT TA3LCDE DRVOSCH EMCCR0 EMC Control Register 0 Protection LCDC Always write Always 1: fc is fc oscillator fs oscillator flag Source clk write 0 external drivability drivability 0: OFF 0: 32KHz clock.
Page 265 TMP91C815 8-Bit Timer (7−1) TMRA01 Symbol Name Address TA0RDE I2TA01 TA01PRUN TA1RUN TA0RUN TA01− Timer 100H Double IDLE2 8-Bit Timer Run/Stop control Buffer 0: Stop 0: Stop & Clear 0: Disable 1: Operate 1: Run (count up) 1: Enable − 8-Bit 102H TA0REG...
Page 266 TMP91C815 (8) UART/Serial Channel (1/2) (8-1) UART/SIO Channel 0 Symbol Name Address Serial RB7/TB7 RB6/TB6 RB5/TB5 RB4/TB4 RB3/TB3 RB2/TB2 RB1/TB1 RB0/TB0 Channel 0 200H SC0BUF R (Receiving)/W (Transmission) Buffer Undefined EVEN OERR PERR FERR SCLKS R (Cleared to 0 by reading) Serial SC0CR Channel 0...
Page 267 TMP91C815 UART/Serial Channel (2/2) (8-3) UART/SIO Channel1 Symbol Name Address Serial RB7/TB7 RB6/TB6 RB5/TB5 RB4/TB4 RB3/TB3 RB2/TB2 RB1/TB1 RB0/TB0 SC1BUF Channel 1 208H R (Receiving)/W (Transmission) Buffer Undefined EVEN OERR PERR FERR SCLKS R (Cleared to 0 by reading) Serial SC1CR Channel 1 209H...
Page 268 TMP91C815 CBUS/Serial Interface Symbol Name Address SCK2 SCK1 SCK0 SBI0CR1 Serial Bus 240H /SWRMON Interface (I2C Bus Control Mode) Register 1 Acknowledge Number of transfer bits Setting for the devisor value n Mode 000: 8, 001: 1, 010: 2 000: 4, 001: 5, 010: 6 0: Disable 011: 3, 100: 4, 101: 5 011: 7, 100: 8, 101: 9...
Page 269 TMP91C815 (10) A/D Converter Symbol Name Address − EOCF ADBF ITM1 ITM0 REPEAT SCAN MODE 2B0H ADMOD Reg0 1: End 1: busy Interrupt in Repeat Mode 1: Repeat 1: Scan 1: Start VREFON I2AD ADTRGE ADCH2 ADCH1 ADCH0 MODE 2B1H ADMOD Reg1 1: VREF...
Page 270 TMP91C815 (11) Watchdog Timer Symbol Name Address  WDTE WDTP1 WDTP0 I2WDT RESCR WDMOD MODE 300H 00: 2 1: WDT IDLE2 1: RESET Always write 01: 2 Enable 0: Abort connect 10: 2 1: Operate internally 11: 2 WDT out to Reset ...
Page 271: Rtc
TMP91C815 (12) RTC (Real-Time Clock) Symbol Name Address SECR Second 320H Undefined “0” 40 sec. 20 sec. 10 sec. 8 sec. 4 sec. 2 sec. 1 sec. MINR Minute 321H Undefined “0” 40 min. 20 min. 10 min. 8 min. 4 min.
Page 272 TMP91C815 (13) Melody/Alarm Generator Symbol Name Address Alarm – Pattern 330H Alarm –Pattern set ALMINV MELALM Melody/ MEL-A 331H Alarm Control Always write 0 Free-run counter Control Alarm Output Frequency 00: Hold Frequency Alarm 01: Restart Invert 1: Melody 10: Clear 1: Invert 11: Clear &...
Page 273 TMP91C815 (14) MMU Symbol Name Address L0EA22 L0EA21 L0EA20 LOCAL0 LOCAL 350H Control 0: Disable LOCAL0 area BANK set 1: Enable L1EA23 L1EA22 L1EA21 LOCAL LOCAL1 351H Control 0: Disable LOCAL1 area ANK set 1: Enable L2EA23 L2EA22 L2EA21 LOCAL2 LOCAL Control 352H...
Page 274: Lcd Controller
TMP91C815 (15) LCD CONTROLLER Symbol Name Address SAL15 SAL14 SAL13 SAL12 TEST MODE LCDSAL LCD Start 360H Address Reg-L Start Address Always SR mode: A15 to A12 Mode write 0 0: RAM 1: SR SAL23 SAL22 SAL21 SAL20 SAL19 SAL18 SAL17 SAL16 LCDSAH...
Page 275 TMP91C815 6. Points to Note and Restrictions (1) Notation The notation for built-in / I/O registers is as follows register symbol <bit symbol> e.g.) TA01RUN <TA0RUN> denotes bit TA0RUN of register TA01RUN. Read-modify-write instructions An instruction in which the CPU reads data from memory and writes the data to the same memory location in one instruction.
Page 276 TMP91C815 (2) Points to note AM0 and AM1 pins This pin is connected to the VCC or the VSS pin. Do not alter the level when the pin is active. EMU0 and EMU1 Open pins. Reserved address areas The TMP91C815 does not have any reserved areas. Warm-up counter The warm-up counter operates when STOP Mode is released, even if the system is using an external oscillator.
Page 277 TMP91C815 128 pin QFP (Flat Package) PACKAGE NAME: TQFP128-P-1414-0.4 16.0±0.2 Unit：mm 14.0±0.1 0.8TYP +0.05 0.105 -0.04 0.8TYP 0.105 M 0.08 15.0±0.2 0~10 ° 0.45~0.75 91C815-274...

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