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prescaler
φT0
2
4
8
φT2
Serial clock generation circuit
BR1CR
<BR1CK1, BR1CK0>
<BR1S3 to
BR1S0>
φ
T0
φ
T2
φ
T8
φ
T32
f
SYS
SCLK1
concurrent
with PC5
I/O Interface Mode
SCLK1
concurrent
with PC5
Receive
Counter
(UART only ÷ 16)
RXDCLK
SC1MOD0
Receive
<RXE>
Control
Receive Buffer1 (shift register)
RXD1
concurrent
with PC4
RB8
Receive buffer2 (SC1BUF)
16 32 64
φT8
φT32
TA0TRG
(from TMRA0)
BR1CR
BR1ADD
<BR1K3 to
BR1K0>
BR1CR
<BR1ADDE>
Baud rate
<SC1, SC0>
generator
÷2
SC1MOD0
Serial Channel
Interrupt
<WU>
Control
SC1CR
<PE>
<EVEN>
Parity Control
Error flag
SC1CR
<OERR><PERR><FERR>
Internal bus
Figure 3.9.3 Block diagram of the Serial Channel 1(SIO1)
91C815-
UART
Mode
SIOCLK
SC1MOD0
SC1MOD0
<SM1, SM0>
I/O
interface mode
SC1CR
<IOC>
Transmision
counter
(UART only ÷ 16)
TXDCLK
Transmission
Control
Transmission Buffer (
TB8
123
TMP91C815
INT request
INTRX1
INTTX1
CTS
1
concurrent
with PC5
SC1MOD0
<CTSE>
SC1BUF)
TXD1
concurrent
with PC3
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