Toshiba TMP91C815F Data Book page 44

16bit micro controller tlcs-900/l1 series
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Three micro DMA transfer modes are supported: 1-byte transfer, 2-byte (one-word) transfer, and
4-byte transfer. After a transfer in any mode, the transfer source / destination addresses are
increased, decreased, or remain unchanged.
This simplifies the transfer of data from I/O to memory, from memory to I/O , and from I/O to I/O.
For details of the transfer modes, see 3.4.2 (4) "Transfer Mode Register". As the transfer counter is
a 16-bit counter, micro DMA processing can be set for up to 65536 times per interrupt source.(The
micro DMA processing count is maximized when the transfer counter initial value is set to 0000H.)
Micro DMA processing can be started by the 24 interrupts shown in the micro DMA start vectors
of Table 3.4.1 and by the micro DMA soft start, making a total of 25 interrupts.
Figure 3.4.2 shows the word transfer micro DMA cycle in transfer destination address INC mode
(except for Counter mode, the same as for other modes).
(The conditions for this cycle are based on an external 16-bit bus, 0 waits, trandfer
source/transfer destination addresses both even-numberd values).
1 state
DM1
DM2
X1
A0 to 23
Next
RD
WR
HWR
/
D0 to 15
States 1~3:
Instruction fetch cycle (gets next address code).
If 3 bytes and more instruction codes are inserted in the instruction queue
buffer, this cycle becomes a dummy cycle.
States 4~5:
Micro DMA read cycle
State 6: Dummy cycle (the address bus remains unchanged from state 5)
States 7~8:
Micro DMA write cycle
(note1): If the source address area is an 8-bit bus, it is increased by two states.
If the source address area is a 16-bit bus and the address starts from an odd number, it is increased by
two states.
(note2): If the destination address area is an 8-bit bus, it is increased by two states.
If the destination address area is a 16-bit bus and the address starts from an odd number, it is
increased by two states.
(note1)
DM3
DM4
DM5
DM6
Trasfer source address
Input
Figure 3.4.2 Timing for micro DMA cycle
91C815-
(note2)
DM7
DM8
Trasger destination
address
Output
41
TMP91C815
Next + 2

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