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3.3.2
SFR
7
SYSCR0
bit Symbol
XEN
(00E0H)
Read/Write
After reset
1
High-frequen
cy oscillator
(fc)
0: Stop
1: Oscillation
Function
7
SYSCR1
bit Symbol
(00E1H)
Read/Write
After reset
Function
7
SYSCR2
bit Symbol
(00E2H)
Read/Write
After reset
Function
(note1) By Reset, low-frequency oscillator is enable.
(note2) In case of using built-in SBI circuit, it must set SYSCR0<PRCK1:0> to '00'.
6
5
4
XTEN
RXEN
RXTEN
1
1
0
Low-frequen
High-frequen
Low-frequen
cy oscillator
cy oscillator
cy oscillator
(fs)
(fc) after
(fs) after
release of
release of
0: Stop
Stop Mode
Stop Mode
1: Oscillation
0: Stop
0: Stop
1: Oscillation
1: Oscillation
6
5
4
6
5
4
SCOSEL
WUPTM1
WUPTM0
R/W
R/W
R/W
0
1
0
0: fs
Warm-Up Timer
1: f
00: reserved
SYS
8
01: 2
/inputted frequency
14
10:2
16
11:2
Figure 3.3.3 SFR for system clock
91C815-15
3
2
RSYSCK
WUEF
PRCK1
R/W
0
0
Selects clock
Warm-up
Select prescaler clock
after release
Timer
00: f
FPH
of Stop
0: Write
01: reserved
Mode
10: fc/16
Don't care
0: fc
11: reserved
1: Write
1: fs
start timer
0: Read
end warm-up
1: Read
do not end
warm-up
3
2
SYSCK
GEAR2
GEAR1
R/W
0
1
Select
Select gear value of high frequency (fc)
system clock
000: fc
0: fc
001: fc/2
1: fs
010: fc/4
011: fc/8
100: fc/16
101: (reserved)
110: (reserved)
111: (reserved)
3
2
HALTM1
HALTM0
SELDRV
R/W
R/W
R/W
1
1
HALT mode
<DRVE>
00: reserved
mode
01: STOP mode
select
10: IDLE1 mode
0: STOP
11: IDLE2 mode
1: IDLE1
TMP91C815
1
0
PRCK0
0
0
1
0
GEAR0
0
0
1
0
DRVE
R/W
0
0
Pin state
control in
STOP mode
0: I/O off
1: Remains
the state
before
HALT
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