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4.5
Serial Channel Timing (I/O Internal Mode)
(1) SCLK Input Mode
Symbol
Parameter
T
SCLK Period
SCY
Output Data
→ SCLK
T
OSS
Rising/Falling
Edge*
SCLK Rising/Falling Edge*
T
OHS
→ Output Data Hold
SCLK Rising/Falling Edge*
T
HSR
→ Input Data Hold
SCLK Rising/Falling Edge*
T
SRD
→ Valid Data Input
Valid Data Input →
T
RDS
SCLK Rising/Falling Edge*
(2) SCLK Output Mode
Symbol
Parameter
T
SCLK Period
SCY
Output Data → SCLK Rising
T
OSS
SCLK Rising/Falling Edge*
T
OHS
→ Output Data Hold
SCLK Rising/Falling Edge*
T
HSR
→ Input Data Hold
SCLK Rising/Falling Edge*
T
SRD
→ Valid Data Input
Valid Data Input →
T
RDS
SCLK Rising/Falling Edge*
(note): SCLK Rinsing/Falling Edge : The rising edge is used in SCLK Rising Mode.
27MHz and 10MHz values are calculated from t
SCLK
Output Mode/
Input Mode
SCLK
(Input Mode)
OUTPUT DATA
TxD
INPUT DATA
RxD
Variable
Min
16X
/2 − 4X − 110
Vcc=3V±10％
t
SCY
/2 − 4X − 180
Vcc=2V±10％
t
SCY
t
/2 + 2X + 0
SCY
3X + 10
0
Variable
Min
16X
/2 − 40
t
SCY
/Falling Edge*
/2 − 40
t
SCY
0
1X + 180
The falling edge is used in SCLK Falling Mode.
SCY
t
SCY
t
t
OSS
OHS
0
0
Valid
91C815-
10 MHz
Max
Min
Max
1.6
290
220
1000
310
− 0
t
1600
SCY
0
10 MHz
Max
Min
Max
8192X
1.6
819
760
760
0
− 1X − 180
t
1320
SCY
280
=16X case.
1
t
RDS
t
t
SRD
HSR
1
Valid
Valid
242
TMP91C815
27 MHz
Unit
Min
Max
µ s
0.59
38
ns
---
ns
370
ns
121
ns
592
ns
0
ns
27 MHz
Unit
Min
Max
µ s
0.59
303
256
ns
256
ns
0
ns
375
ns
217
ns
2
3
2
3
Valid
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