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3.9.2
Operation of each circuit
(1) Prescaler
There is a 6-bit prescaler for generating a clock to SIO0. The clock selected using
SYSCR<PRCK1:PRCK0> is divided by 4 and input to the prescaler as PHI_T0. The prescaler can
be run by selecting the baud rate generator as the serial transfer clock.
Table 3.9.2 shows prescaler clock resolution into the baud rate generator.
Table 3.9.2 Prescaler Clock Resolution to Baud Rate Generator
Select System
Select Prescaler
Clock
<SYSCK>
1 (fs)
0 (fc)
(note): X = Don't care; "−" = Cannot be used
The Baud Rate Generator selects between 4 clock inputs : φT0, φT2, φT8, and φT32 among the
prescaler outputs.
Gear Value
Clock
<GEAR2 to
<PRCK1 to
GEAR0>
PRCK0>
XXX
000 (fc)
fc
001 (
/ 2 )
00
fc
(f
)
010 (
/ 4 )
FPH
fc
011 (
/ 8 )
fc
100 (
/ 16 )
10
XXX
fc
(
/ 16 clock)
91C815-124
Prescaler Output Clock Resolution
φT0
φT2
φT8
fs
fs
fs
/ 2
/ 2
/ 2
2
4
6
fc
fc
fc
/ 2
/ 2
/ 2
2
4
6
fc
fc
fc
/ 2
/ 2
/ 2
3
5
7
fc
fc
fc
/ 2
/ 2
/ 2
4
6
8
fc
fc
fc
/ 2
/ 2
/ 2
5
7
9
fc
fc
fc
/ 2
/ 2
/ 2
6
8
10
fc
fc
/ 2
/ 2
8
10
―
TMP91C815
φT32
fs
/ 2
8
fc
/ 2
8
fc
/ 2
9
fc
/ 2
10
fc
/ 2
11
fc
/ 2
12
fc
/ 2
12
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