Toshiba TMP91C815F Data Book page 35

(3) Operation
A. IDLE2 Mode
In Idle2 Mode only specific internal I/O operations, as designated by the Idle2 Setting Register,
can take place. Instruction execution by the CPU stops.
Figure 3.3 6 illustrates an example of the timing for clearance of the Idle2 Mode Halt state by an
interrupt.
X1
A0 ∼ 23
N e x t
D0 ∼ 15
RD
WR
Interrupt for
release
Figure 3.3.6 Timing chart for Idle2 Mode Halt state cleared by interrupt
B. IDLE1 Mode
In Idle1 Mode, only the internal oscillator and the RTC,MLD continue to operate. The system
clock in the MCU stops. The pin status in the IDLE1 mode is depended on setting the register
SYSCR2<SELDRV,DRVE>. Table 3.3 6 summarizes the state of these pins in the IDLE mode1.
In the Halt state, the interrupt request is sampled asynchronously with the system clock; however,
clearance of the Halt state (i.e. restart of operation) is synchronous with it.
Figure 3.3 7 illustrates the timing for clearance of the Idle1 Mode Halt state by an interrupt.
X1
A0 ∼ 23
N e x t
D0 ∼ 15
RD
WR
Interrupt
for release
Figure 3.3.7 Timing chart for Idle1 Mode Halt state cleared by interrup
Data
IDLE2
mode
Data
IDLE1 mode
91C815-32
TMP91C815
N e x t + 2
Data
N e x t + 2
Data