Toshiba TMP91C815F Data Book page 165

The TMP91C815F compares the levels on the bus's SDA line with those of the internal SDA
output on the rising edge of the SCL line. If the levels do not match, arbitration is lost and
SBI0SR<AL> is set to "1".
When SBI0SR<AL> is set to "1", SBI0SR<MST,TRX> are cleared to "00" and the mode is
switched to Slave Receiver Mode.
SBI0SR<AL> is cleared to "0" when data is written to or read from SBI0DBR or when data is
written to SBI0CR2.
Internal 1
SCL output
Master
A
Internal
D7A
SDA output
Internal
1
SCL output
Master
B
Internal
D7B
SDA output
<AL>
<MST>
<TRX>
Accessed to
SBI0DBR or SBI0CR2
Figure 3.10.12 Example of when TMP91CW12 is a Master Device B
(11) Slave address match detection monitor
SBI0SR<AAS> is set to "1" in Slave Mode, in Address Recognition Mode (i.e. when
I2C0AR<ALS> = "0"), when a GENERAL CALL is received, or when a slave address matches the
value set in I2C0AR. When I2C0AR<ALS> = "1", SBI0SR<AAS> is set to "1" after the first word
of data has been received. SBI0SR<AAS> is cleared to "0" when data is written to or read from the
data buffer register SBI0DBR.
(12) GENERAL CALL detection monitor
SBI0SR<AD0> is set to "1" in Slave Mode, when a GENERAL CALL is received (all 8-bit
received data is "0", after a start condition). SBI0SR<AD0> is cleared to "0" when a start condition
or stop condition is detected on the bus.
(13) Last received bit monitor
The SDA line value stored at the rising edge of the SCL line is set to the SBI0SR<LRB>. In the
acknowledge mode, immediately after an INTS2 interrupt request is generated, an acknowledge
signal is read by reading the contents of the SBI0SR<LRB>.
2 3 4 5 6
D6A D4A D3A D2A
Stop the clock pulse
2 3 4
D6B
Keep Internal SDA output to high-level as losing arbitration
(D7A = D7B, D6A = D6B)
91C815-162
7 8 9 1
D1A D0A D7A' D6A' D5A' D4A'
TMP91C815
2 3 4