Power Management
Two registers can be used to manage power consumption over the acquisition cycle and during idle time
between measurements. Bit positions 03 of the Mode Control Register [4] control the power state
automatically entered after the completion of an acquisition while Power Control Register [101] sets the
present power saving state without requiring a distance measurement. The table below summarizes the
control bits of register 4 associated with power management.
Control Register #4 (0x04) – Mode Control (control_reg[4]:)
Bit
Function
Bit 7 Velocity
Bit 6 Inhibit Reference
Bit 5 Velocity Scale factor
Bit 4 N/A
Bit 3 DET OFF
Bit 2 FPGA SLEEP
Bit 1 CLK SHUT
Bit 0 Preamp Off
Notes:
Default Value : 0x00
●
Preamp Off : Shutdown preamp between measurements
●
●
CLK SHUT : External Clock Shutdown – Not used in standard LidarLite
●
FPGA SLEEP : Full FPGA sleep after measurement
●
DET OFF : Turns off detector bias after measurement
Control Register #101 (0x65) (control_reg [101]:)
Bit
Function
Bit 7
LIDARLite v1 "Silver Label" Manual , Updated: 08/13/15