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I2C Protocol Summary
LIDARLite has a 2wire I2Ccompatible serial interface (refer to I2CBus Specification, Version 2.1, January
2000, available from Philips Semiconductor). It can be connected to an I2C bus as a slave device, under
the control of an I2C master device. It supports standard 100 kHz data transfer mode. Support is not
provided for 10bit addressing.
The Sensor module has a 7bit slave address with a default value of 0x62 in hexadecimal notation. The
effective 8 bit I2C address is: 0xC4 write, 0xC5 read. The unit will not presently respond to a general call.
The I2C serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a start condition, which is when a hightolow
transition on the SDA line occurs while SCL is high. The following byte is the address byte, which
consists of the 7bit slave address followed by a read/write bit with a zero state indicating a write
request. A write operation is used as the initial stage of both read and write transfers. If the slave
address corresponds to the module's address the unit responds by pulling SDA low during the ninth
clock pulse (this is termed the acknowledge bit). At this stage, all other devices on the bus remain
idle while the selected device waits for data to be written to or read from its shift register.
2. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by
an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and
remain stable during the high period of SCL.
3. An 8 bit data byte following the address loads the I2C control register with the address of the first
control register to be read along with flags indicating if auto increment of the addressed control
register is desired with successive reads or writes; and if access to the internal micro or external
correlation processor register space is requested. Bit locations 5:0 contain the control register
address while bit 7 enables the automatic incrementing of control register with successive data
blocks. Bit position 6 selects correlation memory external to the microcontroller if set. (Presently an
advanced feature)
4. If a read operation is requested, a stop bit is issued by the master at the completion of the first data
frame followed by the initiation of a new start condition, slave address with the read bit set (one
state). The new address byte is followed by the reading of one or more data bytes succession.
After the slave has acknowledged receipt of a valid address, data read operations proceed by the
master releasing the I2C data line SDA with continuing clocking of SCL. At the completion of the
receipt of a data byte, the master must strobe the acknowledge bit before continuing the read cycle.
5. For a write operation to proceed, Step 3 is followed by one or more 8 bit data blocks with
acknowledges provided by the slave at the completion of each successful transfer. At the
completion of the transfer cycle a stop condition is issued by the master terminating operation.
Note: The unit responds to read or write requests with a NACK when the sensor is busy processing a
command or performing a measurement. For proper operation the I2C peripheral driver needs to handle the
NACK condition without producing an error condition.
LIDARLite v1 "Silver Label" Manual , Updated: 08/13/15
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