Notes
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Controls M aximum Aquisition Count
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Default Value: 0x80
Range: 0x000xFF (0255).
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Control the FPGA maximum signal integration time.
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Stronger signal results in reduced acquisition count to prevent internal register overflow.
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Sig overflow flag and Ref overflow flag in control register 1 are set when automatic limiting occurs.
Control Register #3(0x03) (control_reg [3]:)
Bit
Bits 74 Stop address (default 5 corresponding to 512)
Bits 30 Start address (default 1 corresponding to 64)
Notes
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control_reg[0x51]: Correlation start and stop locations used for signal acquisition (write only)
Start address: Value in the range from 0x000x0f – starting point in correlation record (record
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broken into 64 element segments 1024 total
Stop address: Value in the range from 0x000x0f – stopping point in correlation record
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With longer correlation records, burst pulse period is roughly proportional to the length of the
correlation record. Unnecessarily long record length increases the probability of false detection
Control Register #4 (0x04) – Mode Control (control_reg[4]:)
Bit
Function
Bit 7 Velocity
Bit 6 Inhibit Reference
Bit 5 Velocity Scale factor
Bit 4 N/A
Bit 3 DET OFF
Bit 2 FPGA SLEEP
Bit 1 CLK SHUT
Bit 0 Preamp Off
Notes:
Default Value : 0x00
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LIDARLite v1 "Silver Label" Manual , Updated: 08/13/15
Function