Detailed Register Descriptions – Internal
Unless otherwise noted, all registers contain one byte and are read and write.
Control Register #0 (0x00) (control_reg[0]:)
Notes
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Command Register
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Write 0x00 to Register 0x00 : Reset FPGA. Reloads FPGA from internal Flash memory – all
registers return to default values
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Write 0x01 to Register 0x00: Correlation processing without new acquisition – used to process
delay of second peak after bit 0 in control register 0x4b is set to 1
Write 0x02 to Register 0x00: Process correlation without new acquisition – used to reprocess
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Write 0x03 to Register 0x00: Take acquisition & correlation processing without DC correction
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Write 0x04 to Register 0x00: Take acquisition & correlation processing with DC correction
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Control Register #1 (0x01) Mode/Status (control_reg[1]:)
Bit
Function
Bit 7
Eye Safe
Bit 6
External Trigger
Complete
Bit 5
Velocity
complete
Bit 4
Secondary
return
Bit 3
Signal not valid Indicates that the signal correlation peak is equal to or below
Bit 2
Sig overflow
flag
Bit 1
Ref overflow
flag
Bit 0
Health*
*Health status indicates that the preamp is operating properly, transmit power is active and a reference
pulse has been processed and has been stored.
Control Register #2 (0x02) (control_reg[2]:)
LIDARLite v1 "Silver Label" Manual , Updated: 08/13/15
This bit will go high if eyesafety protection has been activated
External measurement performed
Velocity measurement completed
Secondary return detected above correlation noise floor threshold
correlation record noise threshold
Overflow detected in correlation process associated with a signal
acquisition
Overflow detected in correlation process associated with a
reference acquisition
"1" state indicates that all health monitoring criteria were met on the
last acquisition. "0" possible problem
Notes