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Bit 6
Bit 5
Bit 4
Bit 3 Det Bias Disable
Bit 2 SLEEP
Bit 1 RCVR PWR
Disable
Bit 0 OSC Disable
Notes:
●
Default Value : 0x00
●
control_reg [65]: Power control (write only)
●
OSC Disable : Disables oscillator reference – Not used in LIDARLite SPC
RCVR PWR Disable : Turns on receiver regulator – decreases power consumption by 30 mA when
●
inhibited
SLEEP : Processor sleep – Reduces power to 20 mA with other hardware disabled
●
(wakes on I2C transaction) Send dummy prior to any command or register access operation.
●
Det Bias Disable : Turns off detector bias charge pump
At the completion of a normal distance measurement or at the completion of the two measurements
associated with a velocity measurement , the first 4 bits of register 4 are loaded into the Power Control
register 101. Loading values into register 101 results in immediate action execution. The loading of the
Power Control register occurs after completion of the reading of the lower byte of the distance measurement
register 16. When pulling data from the unit after a measurement, read all other registers before reading
register 16. Placing the FPGA into a sleep state results in shutting down of all internal clocks making the
internal registers unavailable until the system is awakened. The system will automatically wake from the
sleep state if a read operation is initiated using the I2C interface. A dummy read command should be sent
to the unit to wake it, followed after roughly 10 ms with the desired read or write command. A measurement
initiated by a write to command register 0 will return the system to full power operation prior to a
measurement, followed by a return to a sleep state afterwards. Depending on the bit status various
degrees of power savings are possible, however larger power savings increase the time necessary for the
system to return to normal operation.
Power Saving Mode
Nominal Power Draw 80 mA
LIDARLite v1 "Silver Label" Manual , Updated: 08/13/15
Saving
Wakeup Time
s
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