Notes
Reset [Write Only]: FPGA Core reset – any write to this register
●
●
Soft reset of system always occurs with write to register.
Control Register #93 (0x5d) (control_reg [93]:)
Notes
●
Correlation sign bit [Read Only]: MSB of 9 bit signed result
●
Most significant bit of signed correlation value
Control Register #93 (0x5f) (control_reg [95]:)
Notes
●
Measured transmit power [Read Only]: Using internal power monitor
Control Register #96 (0x60) (control_reg [96]:)
Notes
●
Fine delay [Read Only]: Interpolated fine delay (029)
Control Register #97 (0x61) (control_reg [97]:)
Notes
●
Peak Index high byte [Read Only]: Coarse crossing point in the correlation record prior to zero
crossing
Control Register #98 (0x62) (control_reg [98]:)
Notes
Peak Index low byte [Read Only]: Coarse crossing point in the correlation record prior to zero
●
crossing
Control Register #99 (0x63) (control_reg [99]:)
Notes
●
Positive Crossing Upper correlation pulse data value prior to zero crossing
●
Used to interpolate fine delay
LIDARLite v1 "Silver Label" Manual , Updated: 08/13/15