Control Registers; Wdt Clock Control Register; Wdt Control Register - Epson S1C17W18 Technical Manual

8.4 Control Registers

WDT Clock Control Register

Register name Bit
WDTCLK 15–9 –
8
7–6 –
5–4 CLKDIV[1:0]
3–2 –
1–0 CLKSRC[1:0]
Bits 15–9 Reserved
Bit 8 DBRUN
This bit sets whether the WDT operating clock is supplied in DEBUG mode or not.
1 (R/WP): Clock supplied in DEBUG mode
0 (R/WP): No clock supplied in DEBUG mode
Bits 7–6 Reserved
Bits 5–4 CLKDIV[1:0]
These bits select the division ratio of the WDT operating clock (counter clock). The clock frequency
should be set to around 256 Hz.
Bits 3–2 Reserved
Bits 1–0 CLKSRC[1:0]
These bits select the clock source of WDT.
WDTCLK.
CLKDIV[1:0] bits
0x3
0x2
0x1
0x0
(Note) The oscillation circuits/external input that are not supported in this IC cannot be
selected as the clock source.

WDT Control Register

Register name Bit
WDTCTL 15–10 –
9
8
7–5 –
4
3–0 WDTRUN[3:0]
Bits 15–10 Reserved
Bit 9 NMIXRST
This bit sets the WDT operating mode.
1 (R/WP): NMI mode
0 (R/WP): Reset mode
This bit is used to select whether an NMI signal or a reset signal is output when WDT has not been
reset within the NMI/reset generation cycle.
S1C17W18 TECHNICAL MANUAL
(Rev. 1.2)
Bit name Initial
0x00
DBRUN 0
0x0
0x0
0x0
0x0
Table 8.4.1 Clock Source and Division Ratio Settings
0x0
IOSC
1/16,384
1/8,192
1/4,096
1/2,048
Bit name Initial
0x00
NMIXRST 0
STATNMI 0
0x0
WDTCNTRST 0
0xa
Seiko Epson Corporation
Reset R/W
– R –
H0 R/WP
– R
H0 R/WP
– R
H0 R/WP
WDTCLK.CLKSRC[1:0] bits
0x1 0x2
OSC1 OSC3
1/128 1/16,384
1/8,192
1/4,096
1/2,048
Reset R/W
– R –
H0 R/WP
H0 R
– R
H0 WP Always read as 0.
H0 R/WP –
8 WATCHDOG TIMER (WDT)
Remarks
0x3
EXOSC
1/1
Remarks
8-3