Clg Fout Control Register - Epson S1C17W18 Technical Manual

2 POWER SUPPLY, RESET, AND CLOCKS
Bits 15–6 Reserved
Bit 5 OSC1STPIE
Bit 4 IOSCTEDIE
These bits enable the OSC1 oscillation stop and IOSC oscillation auto-trimming completion inter-
rupts.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
Each bit corresponds to the interrupt as follows:
CLGINTE.OSC1STPIE bit: OSC1 oscillation stop interrupt
CLGINTE.IOSCTEDIE bit: IOSC oscillation auto-trimming completion interrupt
Bit 3 Reserved
Bit 2 OSC3STAIE
Bit 1 OSC1STAIE
Bit 0 IOSCSTAIE
These bits enable the oscillation stabilization waiting completion interrupt of each clock source.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
Each bit corresponds to the clock source as follows:
CLGINTE.OSC3STAIE bit: OSC3 oscillator circuit
CLGINTE.OSC1STAIE bit: OSC1 oscillator circuit
CLGINTE.IOSCSTAIE bit: IOSC oscillator circuit

CLG FOUT Control Register

Register name Bit
CLGFOUT 15–8 –
7
6–4 FOUTDIV[2:0]
3–2 FOUTSRC[1:0]
1
0
Bits 15–7 Reserved
Bits 6–4 FOUTDIV[2:0]
These bits set the FOUT clock division ratio.
Bits 3–2 FOUTSRC[1:0]
These bits select the FOUT clock source.
CLGFOUT.
FOUTDIV[2:0] bits
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Note: When the CLGFOUT.FOUTSRC[1:0] bits are set to 0x3, the FOUT output will be stopped in
SLEEP/HALT mode as SYSCLK is stopped.
Bit 1 Reserved
2-24
Bit name Initial
0x00
– 0
0x0
0x0
– 0
FOUTEN 0
Table 2.6.13 FOUT Clock Source and Division Ratio Settings
0x0
IOSCCLK
1/128
1/64
1/32
1/16
1/8
1/4
1/2
1/1
Seiko Epson Corporation
Reset R/W
– R –
– R
H0 R/W
H0 R/W
– R
H0 R/W
CLGFOUT.FOUTSRC[1:0] bits
0x1 0x2
OSC1CLK OSC3CLK
1/32,768 1/128
1/4,096 1/64
1/1,024 1/32
1/256 1/16
1/8 1/8
1/4 1/4
1/2 1/2
1/1 1/1
Remarks
0x3
SYSCLK
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1/1
S1C17W18 TECHNICAL MANUAL
(Rev. 1.2)