Epson S1C17W18 Technical Manual page 29

3. When the slp instruction is executed in normal mode (all the clocks are configured to stop during SLEEP)
The hardware switches to economy mode at the same time the CPU enters SLEEP mode. The PWGINTF.
MODCMPIF bit is not set.
4. When the slp instruction is executed in normal mode (only OSC1 operates during SLEEP)
After a lapse of 1 ms from transition to SLEEP mode, the hardware switches from normal mode to econo-
my mode and sets the PWGINTF.MODCMPIF bit to 1.
5. When the CPU wakes up from SLEEP state
At the same time the CPU enters RUN mode, the hardware switches to economy mode when OSC1 only is
operating or to normal mode in other conditions.
For the PWGINTF.MODCMPIF bit set conditions, refer to "Interrupts."
Super economy mode
Super economy mode uses a charge pump to generate V
operating modes described above. This achieves more power-saving operation in comparison with economy
mode. However, the charge pump operation requires a V
more, super economy mode does not allow use of high-speed clocks (IOSC, OSC3, and EXOSC) because of its
lack of drive capability.
Switching to super economy mode from another mode (automatic mode)
1. Check to see if V
2. Write 0x0096 to the MSCPROT.PROT[15:0] bits.
3. Check to see if the OSC1 oscillation has stabilized (see "Oscillation start procedure for the OSC1 oscil-
lator circuit" in Section 2.3.4.).
4. Stop the high-speed clock sources.
5. Set the PWGTIM.DCCCLK[1:0] bits (first time only). (Set charge pump operating clock division ratio)
6. Set the PWGCTL.PWGMOD[2:0] bits to 0x5.
7. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection)
Notes: • Be sure to avoid setting to super economy mode under the conditions shown below, as it
may cause a runaway CPU.
1. V does not meet the requirement for super economy mode.
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2. A clock source other than OSC1 is operating.
3. OSC1 clock is not stabilized.
• The charge pump operates with the OSC1 clock. Therefore, to put the CPU into SLEEP state
in super economy mode, the clock sources must be configured so that OSC1 only will oper-
ate in SLEEP mode (CLGOSC.OSC1SLPC bit = 0 and other CLGOSC.****SLPC bits = 1).
Switching to automatic mode/economy mode from super economy mode
1. Write 0x0096 to the MSCPROT.PROT[15:0] bits.
2. Set the PWGCTL.PWGMOD[2:0] bits to 0x0.
Or set the PWGCTL.PWGMOD[2:0] bits to 0x3.
3. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection)
4. Check to see if the PWGINTF.MODCMPIF bit = 1 (mode transition completed).
For the PWGINTF.MODCMPIF bit set conditions, refer to "Interrupts."
Notes: • Be sure to avoid switching to normal mode directly from super economy mode, as it may
cause a malfunction. When using a high-speed clock, first switch to automatic mode before
starting the clock source.
• The PWGINTF.MODCMPIF bit is set to 1 after a lapse of 10 ms from the switching operation
from super economy mode to automatic mode (or economy mode). Do not perform heavy-
load operations, such as starting a high-speed clock source, before the PWGINTF.MODC-
MPIF bit is set to 1, as it may cause a malfunction.
S1C17W18 TECHNICAL MANUAL
(Rev. 1.2)
meets the requirement using the supply voltage detector.
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Seiko Epson Corporation
2 POWER SUPPLY, RESET, AND CLOCKS
that is generated by the linear regulator in the three
D1
voltage that exceeds the prescribed value. Further-
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(Remove system protection)
(Set to super economy mode)
(Remove system protection)
(Set to automatic mode)
(Set to economy mode)
2-3