Epson S1C17W18 Technical Manual page 39

(1) When the CLGSCLK.WUPMD bit = 0
SYSCLK
(CPU operating clock)
(2) When the CLGSCLK.WUPMD bit = 1 and the CLGSCLK.WUPSRC[1:0] bits = 0x0
SYSCLK
(CPU operating clock)
Clock external output (FOUT)
The FOUT pin can output the clock generated by a clock source or its divided clock to outside the IC. This al-
lows monitoring the oscillation frequency of the oscillator circuit or supplying an operating clock to external
ICs. Follow the procedure shown below to start clock external output.
1. Assign the FOUT function to the port.
2. Configure the following CLGFOUT register bits:
- CLGFOUT.FOUTSRC[1:0] bits
- CLGFOUT.FOUTDIV[2:0] bits
- Set the CLGFOUT.FOUTEN bit to 1. (Enable clock external output)
IOSC oscillation auto-trimming function
The auto-trimming function adjusts the IOSCCLK clock frequency by trimming the clock with reference to the
high precision OSC1CLK clock generated by the OSC1 oscillator circuit. Follow the procedure shown below to
enable the auto-trimming function.
1. After enabling the OSC1 oscillation, check if the stabilized clock is supplied (CLGINTF.OSC1STAIF bit =
1).
2. After enabling the IOSC oscillation, check if the stabilized clock is supplied (CLGINTF.IOSCSTAIF bit = 1).
3. Write 0x0096 to the MSCPROT.PROT[15:0] bits. (Remove system protection)
4. If the SYSCLK clock source is IOSC, set the CLGSCLK.CLKSRC[1:0] bits to a value other than 0x0
(IOSC).
5. Write 1 to the CLGINTF.IOSCTEDIF bit.
6. Write 1 to the CLGINTE.IOSCTEDIE bit.
7. Write 1 to the CLGIOSC.IOSCSTM bit.
8. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection)
9. The trimmed IOSCCLK can be used if the CLGINTF.IOSCTEDIF bit = 1 after an interrupt occurs.
After the trimming operation has completed, the CLGIOSC.IOSCSTM bit automatically reverts to 0. Although
the trimming time depends on the temperature, an average of several 10 ms is required. When IOSCCLK is being
used as the system clock or a peripheral circuit clock, do not use the auto-trimming function.
S1C17W18 TECHNICAL MANUAL
(Rev. 1.2)
OSC1CLK
Executing the
slp instruction
CLGSCLK.CLKSRC[1:0] = 0x1 (OSC1)
CLGSCLK.WUPSRC[1:0] = 0x1 (OSC1)
OSC1CLK
Executing the
slp instruction
CLGSCLK.CLKSRC[1:0] = 0x1 (OSC1)
CLGSCLK.WUPSRC[1:0] = 0x0 (IOSC)
Figure 2.3.4.4 Clock Control Example at SLEEP Cancelation
(Refer to the "I/O Ports" chapter.)
(Select clock source)
(Set clock division ratio)
Seiko Epson Corporation
2 POWER SUPPLY, RESET, AND CLOCKS
SLEEP mode
(CPU stop, CLK stop)
Interrupt
(Wake-up)
∗ Starting up with the same clock as one
that used before SLEEP mode was entered.
SLEEP mode IOSCCLK
(CPU stop, CLK stop) (Unstable)
Interrupt
(Wake-up)
CLGSCLK.CLKSRC[1:0] = 0x0 (IOSC)
CLGSCLK.WUPSRC[1:0] = 0x0 (IOSC)
∗ Switching to IOSC that features fast
initiation allows high-speed processing.
(Clear interrupt flag)
(Enable interrupt)
(Enable IOSC oscillation auto-trimming)
Oscillation stabilization waiting time
OSC1CLK
OSC1CLK
(Unstable)
IOSCCLK
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