Remc2 Interrupt Enable Register; Remc2 Carrier Waveform Register - Epson S1C17W18 Technical Manual

While this bit is set to 1, writing to the REMAPLEN.APLEN[15:0] bits is ineffective.
Bits 7–2 Reserved
Bit 1 DBIF
Bit 0 APIF
These bits indicate the REMC2 interrupt cause occurrence status.
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred
1 (W): Clear flag
0 (W): Ineffective
The following shows the correspondence between the bit and interrupt:
REMINTF.DBIF bit: Compare DB interrupt
REMINTF.APIF bit: Compare AP interrupt
These interrupt flags are also cleared to 0 when 1 is written to the REMDBCTL.REMCRST bit.

REMC2 Interrupt Enable Register

Register name Bit
REMINTE 15–8 –
7–2 –
1
0
Bits 15–2 Reserved
Bit 1 DBIE
Bit 0 APIE
These bits enable REMC2 interrupts.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
The following shows the correspondence between the bit and interrupt:
REMINTE.DBIE bit: Compare DB interrupt
REMINTE.APIE bit: Compare AP interrupt

REMC2 Carrier Waveform Register

Register name Bit
REMCARR 15–8 CRDTY[7:0]
7–0 CRPER[7:0]
Bits 15–8 CRDTY[7:0]
These bits set the high level period of the carrier signal.
The carrier signal is set to high level from the 8-bit counter for carrier generation = 0x00 and it is in-
verted to low level when the counter exceeds the REMCARR.CRDTY[7:0] bit-setting value. The car-
rier signal duty ratio is determined by this setting and the REMCARR.CRPER[7:0] bit-setting. (See
Figure 17.4.3.2.)
Bits 7–0 CRPER[7:0]
These bits set the carrier signal cycle.
A carrier signal cycle begins with the 8-bit counter for carrier generation = 0x00 and ends when the
counter exceeds the REMCARR.CRPER[7:0] bit-setting value. (See Figure 17.4.3.2.)
S1C17W18 TECHNICAL MANUAL
(Rev. 1.2)
Bit name Initial
0x00
0x00
DBIE 0
APIE 0
Bit name Initial
0x00
0x00
Seiko Epson Corporation
17 IR REMOTE CONTROLLER (REMC2)
Reset R/W
– R –
– R
H0 R/W
H0 R/W
Reset R/W
H0 R/W –
H0 R/W
Remarks
Remarks
17-11